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Hitachi AP1 - Page 260

Hitachi AP1
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HD614P080S--------------
The HD614P080S
is
a 4-bit single chip microcomputer
which
has
mounted a standard
EPROM
2764/27128 for pro-
gram memory.
The
HD614P080S
is
pin-compatible with the mask
ROM
type HMCS404C/404AC,
but
has some differences with them
as
shown in Table 33.
By
modifying the program in the EPROM,
it can
be
used for the evaluation
of
the HMCS404C/404AC, or
for
small-scale
production.
• HARDWARE FEATURES
• 4·bit Architecture
• Applicable
to
4k or 8k words x 10 bits
of
EPROM
4096 words x 10 bits
•.•..
HN482764, HN27C64
8192 words x
10 bits
..•.•
HN4827128
•
Data
Memory (RAM) Capacity
••••.••.
576 digits x 4 bits
• 58 I/O Pins - 26
I/O
pins
are
high voltage up
to
40V (max).
• 2 Timer/Counters
11-bit
Prescaler
8-bit
Free
Running Counter
8·bit Auto-reload Timer/Event Counter
• Clocked Synchronous 8-bit
Serial
Interface
•
51nterrupts
External 2
Timer/Counter 2
Serial
Interface 1
• Subroutine Stack
Up
to
16
levels
including interrupts
• Minimum Instruction Execution Time; 1.33
~
• 2 Low Power Modes
Standby - Stops instruction execution while keeping
clock generator
a.nd
interrupt functions in-
cluded
Timer/Counter
and
Serial Interface in
operation
Stop Stops instruction execution
and
clock
genera-
tion while retaining RAM data
• Clock Generator
External Connection
of
Crystal Resonator
or
Ceramic
Filter Resonator (externally drivable)
•
Power Voltage
Range;
5V ±
10%
•
I/O
Pin
Circuit Form
All standard pins
are
"without
pull-up MOS".
All
high voltage pins
are
"without
pull-down MOS".
• Shrink
Type
64
Pin EPROM On-package
• SOFTWARE FEATURES
• Software Compatible
with
HMCS404C/404AC
• Instruction Set Similar
to
and
More Powerful than HMCS40
Series;
99
Instructions
•
High Programming Efficiency
with
10-bit ROM/Word; 79
instructions
are·
single word instructions.
• Direct Branch
to
All
ROM
Area
• Direct or Indirect Addressing
to
All RAM Area
• Subroutine Nesting Up
to
16
Levels
Including Interrupts
HD614P08OS
(DC-64SP)
• PIN ARRANGEMENT
0"
1 0
D"~
D ••
~
01
..
4
D ••
ii
Roo~
Ro.~
Ro,~
Ro.~
R.o~
R"
11
R,. 1
Rll1
R,o
1
R"
1
R22
1
Rn
1
R40
1
R.t/Vdisp 1
R""
RlI 1
R.,fiNTo
R33fiNT,
RIO
R"
Ru
(DVee
([i)00
o
Dt
([)
0,
Ru
7
OGND
RIO
Rot
RI2
Ro.
1
Vee
(Top View)
Vee
@
Vee~
A
..
@
Ao@
A. @
A,,@
GND@
Ato@
CE@
0,
<!}
o.
<!}
Oo@
O.
<!}
O. @
• Binary
and
BCD Arithmetic Operation
• Powerful Logic Arithmetic Operation
0.0
D.
D.
10,
D.
D.
D.
D.
0,
D.
Do
GND
OSC,
10SC.
'fEsT
RESET
RIl
R
..
ROt
RIO
Ro.
Ro,
Rot
1
Roo
Rn
Rn
R7t
R,o
Ro.
Ro,ISO
RotlSl
Roo~
• Pattern Generation - Table Look
Up
Capability -
•
Bit Manipulation
for
Both RAM and
I/O
• VERSATILE PROGRAM DEVELOPMENT SUPPORT
TOOLS
•
H68SD
Series
Macro Assembler
•
H68SD5-use Emulator (With
Real
Time Trace Function)
258