Hitachi AP1 - Page 290

HD614P080S-------------------------------------------------------------
Table 27. Compare Instruction
2
OPERATION MNEMONIC
OPERATION CODe FUNCTION STATUS
YCLE
Immediate Not Equal to Memory
INEM
i
o 0 0 0 lOb i2 h io
i;fM
NZ
1/1
Immediate Not Equal to Memory INEMD
i,d
~.J.~7~'~5~~ ~ ~ ~
i;fM
NZ
2/2
A Not Equal to Memory ANEM
0000000100 A-fM NZ
1/1
A Not Equal to Memory ANEMD d
~.J.~7~ ~ ~~ J2~' &
A;fM
NZ
2/2
B Not Equal to Memory
BNEM
0001000100
B;fM
NZ
1/1
Y Not Equal to Immediate
YNEI
i
000111bhhio
Yi=i NZ
1/1
Immediate less or Equal to Memory IlEM i o 0 0 0 1 1 iJ i2 h io i~M NB
1/1
Immediate less or Equal to Memory
IlEMD
i,d
~.J.~7~.J5~~ ~ ~ ~
i~M
NB
2/2
A less or Equal to Memory AlEM
0000010100 A~M NB
1/1
A less or Equal to Memory AlEMD d
~JJl~7&~.l~lJ'~' &
A~M NB
2/2
B less or Equal to Memory BlEM
0011000100 B~M NB
1/1
A less or Equal to Immediate
AlEI i
1
0 1 0 1 1 i3 i2 h io
A~i NB
1/1
Table 28. RAM 8it Manipulation Instruction
OPERATION MNEMONIC
OPERATION CODE
FUNCTION
2
STATUS
CYCLE
Set Memory Bit
SEM n
00 1 0000 1 nIno
1-M(n)
1/1
Set Memory Bit
SEMD n,d
~.1.17~~§~~312~:~
1-M(n)
2/2
Reset Memory Bit REM n
o 0 1 0 0 0 1 0 nIno
O->M(n)
1/1
Reset Memory Bit
REMD n,d
~. J. J7~' ~5 ~ J3 ~2 ~,'ag
O->M(n)
2/2
Test Memory Bit
TM n
o 0 1 00 0 1 1 nIno
M(n)
1/1
Test Memory Bit
TMD n,d
~9~' ~7 ~6 ~§ ~ ~3 ~2 ~:'Jg
M(n)
2/2
Table 29. ROM Address Instruction
~
OPERATION MNEMONIC OPERATION CODE FUNCTION
STATUS
CYCL
Branch on Status 1 BR b
1 1
b7bebeb~Jb2b,bo
1
1/1
long Branch on Status 1 BRL u
~.~~7~~§~~~~::
1
2/2
Long Jump Unconditionally
JMPl u
~. ~ ~7~' ~§ ~ ~l3tJ2it"~
2/2
Subroutine Jump on Status 1
CAL a
o 1 1 1 a5a4a3a2a,aO
1
1/2
long Subroutine Jump on Status 1
CAll u
~I J. ~7 JI J§ & ~:g:g,'~
1
2/2
Table Branch TBR
p
o 0 1 0 1 1 P3P2P,PO 1/1
Return from Subroutine RTN
0000010000
1/3
Return from Interrupt
RTNI 0000010001
1-I/E 1/3
Table 30. Input/Output Instruction
OPERATION
MNEMONIC
OPERATION CODE
2
FUNCTION
STATUS
YCLE
Set Discrete I/O latch
SED
o 0 1 1 1
00100 1-D(Y)
1/1
Set Discrete I/O latch Direct
SEDD
m
1
0 1
1 1
0
m3m2m,mO 1-D(m)
1/1
Reset Discrete I/O latch
RED
000 1 1
00100 O-D(Y)
1/1
Reset Discrete I/O latch Direct
REDO
m 1
o 0
1 1
0 m3m2m,mO O-D(m)
1/1
Test Discrete I/O latch
TO
o 0
1 1 1
o 0 0 0 0
D(Y)
1/1
Test Discrete I/O latch Direct
TOO
m 1
0
1
0 1
0 m3m2m,mO
D(m)
1/1
load A from R-Port Register
lAR m 1
o 0
1
o 1 m~2m,mO R(m)-A
1/1
load B from R-Port Register
lBR
m
1
0
0
1
o 0 m3m2m,1llo R(m)-B
1/1
load R-Port Register from A
lRA
m 1 0 1 1
o 1 m3m2m,mO A-R(m)
1/1
load R-Port Register from B
lRB
m 1
0 1 1
o 0
m3m2m,1llo
B-R(m)
1/1
Pattern Generation
P p
o 1 1 o 1 1
P3P2P,
Po 1/2
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