--------------------------------------------------------------------------HMCS404AC
o
15
16
63
64
4095
4096
16383
1
I
I
Vector
Address
Zero-Page Subroutine
(64Words)
Program
Pattern
(4096Words)
•
RAM
MEMORY
MAP
$0000
01-
JMPL
Instruction
-
1
(Jump
to
RESET
Routine)
$OOOF
2
JMPL
Instruction
$0010
~
(Jump
to
INTo Routine)
-
3
\
4
JMPL
Instruction
5~
(Jump
to
INT1
Routine)
-
$003i=
6
JMPL
Instruction
$0040
7
~
(Jump
to
TIMER-A Routine) -
81-
JMPL
Instruction
-
9
(Jump
to
TIMER-S Routine)
10
11
SOFFF
12
JMPL
Instruction
$1000
~
-
13
(Jump
to
SERIAL Routine)
14
$3FFF
1~
Fig. 1
ROM
Memory
Map
$0000
$0001
$0002
$
0003
$0004
$0005
$
0006
$
0007
$
0008
$0009
$OOOA
$OOOB
$OooC
$
0000
$
OOOE
$OOOF
MeV
includes 256 digits x 4 bits
RAM
as
the data area and
stack area. In addition
to
these areas, interrupt control bits
and special registers are also mapped on the
RAM
memory
space.
RAM
memory map
is
illustrated in Fig. 2 and described
in the following paragraph.
o
31
32
RAM-mapped Registers
Memory Registers(MR)
$000
$ 01F
$020
\
0
1
Interrupt
Control
8its
2
3
4
Port Mode
Reg.
(PMR)
,
W
47
48
~---------------
----
$ 02F
$
030
,
$000
$001
$002
$003
$004
$005
$006
$
007
$008
$009
$OOA
$008
$OOC
223
224
959
960
1023
Data
( 192Digits)
Not
Used
Stack
(64Digits)
R :Read
Only
W :Write Only
R/W:
Read
/Write
5
Serial
Mode
Reg.
(SMR)
,W
6
Serial Data
Reg.
Lower
(SRL)
:R/W
7
Serial Data
Reg.
Upper
(SRU)
:R/W
8
Timer
Mode
Reg.
A
(TMA)!
W
9 Timer
Mode
Reg.
8
(TMB)
I W
$ODF
10
TIMER-B •
(TCBLlTLRL)
:
R/W
$OEO
~
(TCBU/TLRU):
R/W
11
12
$
3BF
Not
l!sed
$3CO
31
$ 01F
$3FF
* Two registers are mapped on same address.
1
0
Timer
IEvent
Counter
BLower;
R Timer Load
Reg.
Lower
I W $
OOA
~~~~~(T~C~B~L~)~~--_+~~~--~(~T~L~RL~)~~--~~
11
Timer
IEvenh~o~c~er
B
Upper
I R Timer
L(~~R~t
Upper : W $
OOB
Fig. 2
RAM
Memory
Map
307
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