HMCS45C,HMCS45CL------------------------------------------------------
INT,
INTo
IFO,
IF1
: Set has priority over reset.
Figure
20
Interrupt
Circuit Block Diagram
• RESET FUNCTION
The reset
is
performed
by
setting the
RESET
pin
to
"1"
("High" level) and the HMCS45C gets into operation
by
setting
it to
"0"
("Low" level). Refer to Figure
21.
Moreover, the
HMCS45C
has the automatic reset function (ACL; Built-in Reset
Circuit). The Built-in Reset Circuit restricts the rise condition
of
the
power
supply. Refer to Figure
22.
When the Built-in Reset
Circuit
is
used, RESET should
be
connected to V
ss.
Internal state
of
the HMCS45C are specified
as
follows
by
the
(Reset
Statel
Vee
reset function.
Program Counter (PC)
is
set to 3F address on
31
page
(31-
3F).
IIRI, IIRT,
liE
and CF are reset to
"0".
IFO,
IFI and TF are set to
"1".
Reset/Set of I/O latch and register
(Do
to 0
15
,
RO
to
R6) are
set to
"1".
Note that other blocks (Status, Register, Timer/Counter,
RAM, etc.) are not cleared.
(Reset Statel
tfRST
•
tRsn
includes the time required
from
the
power
ON
until the operation gets
into
the constant state .
• tRST2
is
applied when the operation
is
in the constant state.
Figure
21
RESET
Timing
O.2V
Vcc----"I
tOFF
specifies the period when the power supply is
OFF
in the case that a short break
of
the power supply occurs and the
power
supply ON/OFF
is
repeated.
Figure
22
Power Supply
Timing
for
Built-in Reset Circuit
• HALT FUNCTION
When the HLT pin
is
set to
"0"
("Low" level), the internal
clock
stops and
all
the internal statuses (RAM, the Registers, the
Carry F/F, the
Status
F/F,
the Program Counter, and
all
the in-
ternal statuses) are held. Because
all
internal
logic
operation stop,
power consumption
is
reduced. There are
two
input/output
statuses
in
the Halt State. The user should
specify
either "En-
able"
or "Disable" using a mask option at the time
of
ordering
ROM.
"Enable"1output
........
The Status before the Halt State
is
held.
Pull up
MOS
...
ON
76
LInput.
.........
No relation to
"Halt"
Since Pull
up
MOS
is
ON, Pull
up
MOS
current
flows
with output
"0"
("Low" level)
in
the Halt
State (NMOS;ON). When an input signal changes,
transmission current
flows
into an input circuit.
Also, current
flows
into Pull up
MOS.
These cur-
rents are added to the
Stand-by Supply Current
(or Halt Current).
"Disable"
10utput
........
High
Impedance
(NMOS,
PMOS:
OFF)
Pull
up
MOS
...
OFF
Input.
.........
Input Circuit: OFF
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