--------------------------------------------------------HMCS46C,HMCS46CL
• Designation
of
ROM Address and
ROM
Code
The bank
part
of
the
ROM
address is shown
in
the binary
system and the page
part
in the decimal system. The address
part
is divided
into
2 bits and 4 bits,
and
shown
in
the
hexa-
decimal system.
It
is
possible
to
combine the bank
part
and the page
part
and
show the combined
part
as
the Page (in the decimal system).
(a) ROM Address
;----
(Page Part!
~
Bank Part
In this case,
the
0 Page
to
the
31 Page in
the
Bank 1 are shown
as
the
32
Page
to
the 63 Page. The examples are 'shown
in
Figure
3.
One word
(10
bits)
of
ROM is divided
into
three parts (2
bits, 4 bits and 4 bits from
the
most
significant
bit
010 in order)
shown in
the
hexa-decimal system. The examples are shown
in
Figure 3.
/\r-
Page
Part----.'
~Address
Part~
1111:°:1:°:°1
:0:0:1:1:°1
Bank 1
20-26:
Bank 1
20
Page 26 Address
(52-26:
52
Page 26 Address)
'---.I~
Decimal
------1''-----.1
'----
Hexa-
~
Binary
He~a-
decimal
~---(Decimal)
___
~I
decImal
(b) ROM Code
°'0
_0,
° : 1 : 1 : ° : 1 : ° : 1 I
ROM
Pattern, Object Code: 1B5
L Hexa- -1'---Hexa-decimal
~'----
Hexa-decimal---1
decimal
Figure 3 Designation
of
ROM Address and ROM Code
• PATTERN GENERATION
The pattern (constant) can be accessed
by
the
pattern
in-
struction (P). The
pattern
can
be
written in any address
of
the
ROM address
space_
• Reference
ROM addressing for reference
of
the patterns is achieved
by
modifying the program counter
with
the accumulator, the B
register, the
Carry
F/F
and
the
operand p. Figure 4 shows
how
to
modify the program
counter_The
address
part
is replaced
with
the accumulator and the lower 2 bits
of
B register, while
the page
part
and the bank
part
are ORed
with
the
upper 2 bits
of
B register, the Carry F
/F
and the operand p.
The value
of
the operand p
(P2
,
PI,
Po) is 0
to
7 (decimal).
The
bank
part
of
the ROM address
to
be referenced
to
is
determined
by
the logical equation:
PC
ll
+
P2
(P2
= the
MSB
of
the
operand p).
If
the address where the pattern instruction exists is in the
Bank
1,
only the
pattern
of
the Bank 1 can be referenced.
If
the
address where the pattern instruction exists is in the
Bank
0,
the
pattern
of
the either Bank 1
or
Bank 0 can be refer-
enced depending
on
the value
of
P2. The
truth
table
of
the
bank
part
of
the
ROM address is shown in Table 2.
The value
of
the
program counter is apparently modified and
does
not
change actually. After execution
of
the
pattern
instruc-
tion, the program counter counts
up
and the
next
instruction is
91
executed.
The
pattern
instruction
is
executed in 2-cycle time.
• Generation
The
pattern
of
referred ROM address is generated as the fol-
lOwing
two
ways:
(i) The pattern
is
loaded
into
the accumulator and B
register.
(li)
The
pattern
is loaded
into
the Data
I/O
Registers R2
and
R3.
Selection is determined
by
the command bits
(0
9
,
010)
in
the
pattern.
Mode (i) is performed when
0
9
is
"1"
and
mode
(ii)
is per-
formed when 010 is "1
".
Mode (i)
and
(ii)
are simultaneously performed when
both
of
0
9
and 010 are
"1".
The correspondence
of
each
bit
of
the pat-
tern is shown in Figure 5.
Examples
of
the pattern instruction usage is shown in Table
3_
CAUTION
In
the program execution, the pattern can
not
be distinguish-
ed from the instruction. When the program is
executed
at
the
addresses
into
which
pattern
is written, the instruction corres-
ponding
to
the pattern
bit
is executed_ Take care
that
a
pattern
is
not
executed
as
an instruction.
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