The HT48R50A-1/HT48C50-1 and HT48R70A-1/ HT48C70-1 devices have two internal timers,
Timer/Event Counter 0 and Timer/Event Counter 1, and therefore require an additional timer con
-
trol register TMR1C. The HT48RU80/HT48CU80 devices have an additional 8-bit timer
Timer/Event Counter 2 which requires an additional control register TMR2C.
46
I/O Type MCU
T 1 M 1
0
0
1
1
T 1 M 0
0
1
0
1
n o m o d e a v a i l a b l e
e v e n t c o u n t e r m o d e
t i m e r m o d e
p u l s e w i d t h m e a s u r e m e n t m o d e
T i m e r / E v e n t C o u n t e r C o n t r o l R e g i s t e r
T M R 1 C H T 4 8 R 5 0 A - 1 / H T 4 8 C 5 0 - 1
H T 4 8 R 7 0 A - 1 / H T 4 8 C 7 0 - 1
H T 4 8 R U 8 0 / H T 4 8 C U 8 0
N o t i m p l e m e n t e d , r e a d a s " 0 "
E v e n t C o u n t e r a c t i v e e d g e s e l e c t
1 : c o u n t o n f a l l i n g e d g e
0 : c o u n t o n r i s i n g e d g e
P u l s e W i d t h M e a s u r e m e n t a c t i v e e d g e s e l e c t
1 : s t a r t c o u n t i n g o n r i s i n g e d g e , s t o p o n f a l l i n g e d g e
0 : s t a r t c o u n t i n g o n f a l l i n g e d g e , s t o p o n r i s i n g e d g e
T i m e r / E v e n t C o u n t e r c o u n t i n g e n a b l e
1 : e n a b l e
0 : d i s a b l e
N o t i m p l e m e n t e d , r e a d a s " 0 "
O p e r a t i n g m o d e s e l e c t
b 7
T 1 ET 1 O NT 1 M 0T 1 M 1
b 0
T i m e r / E v e n t C o u n t e r C o n t r o l R e g i s t e r
T M R 2 C H T 4 8 R U 8 0 / H T 4 8 C U 8 0
E v e n t C o u n t e r a c t i v e e d g e s e l e c t
1 : c o u n t o n f a l l i n g e d g e
0 : c o u n t o n r i s i n g e d g e
P u l s e W i d t h M e a s u r e m e n t a c t i v e e d g e s e l e c t
1 : s t a r t c o u n t i n g o n r i s i n g e d g e , s t o p o n f a l l i n g e d g e
0 : s t a r t c o u n t i n g o n f a l l i n g e d g e , s t o p o n r i s i n g e d g e
T i m e r / E v e n t C o u n t e r c o u n t i n g e n a b l e
1 : e n a b l e
0 : d i s a b l e
N o t i m p l e m e n t e d , r e a d a s " 0 "
O p e r a t i n g m o d e s e l e c t
T 2 M 1 T 2 M 0
0 0 n o m o d e a v a i l a b l e
0 1 e v e n t c o u n t e r m o d e
1 0 t i m e r m o d e
1 1 p u l s e w i d t h m e a s u r e m e n t m o d e
T i m e r p r e s c a l e r r a t e s e l e c t
T 2 P S C 2
0
0
0
0
1
1
1
1
T 2 P S C 1
0
0
1
1
0
0
1
1
T 2 P S C 0
0
1
0
1
0
1
0
1
T i m e r R a t e
1 : 2
1 : 4
1 : 8
1 : 1 6
1 : 3 2
1 : 6 4
1 : 1 2 8
1 : 2 5 6
b 7
T 2 ET 2 O NT 2 M 0T 2 M 1
b 0
T 2 P S C 2 T 2 P S C 1 T 2 P S C 0