same clock cycle. The RXIF flag is cleared when the USR register is read with RXIF set, followed
by a read from the RXR register, and if the RXR register has no data available.
·
RIDLE
The RIDLE flag is the receiver status flag. When this read only flag is ²0², it indicates that the re
-
ceiver is between the initial detection of the start bit and the completion of the stop bit. When the
flag is ²1², it indicates that the receiver is idle. Between the completion of the stop bit and the de
-
tection of the next start bit, the RIDLE bit is ²1², indicating that the UART is idle.
·
OERR
The OERR flag is the overrun error flag, which indicates when the receiver buffer has over
-
flowed. When this read only flag is ²0² there is no overrun error. When the flag is ²1², an overrun
error occurs which will inhibit further transfers to the RXR receive data register. The flag is
cleared by a software sequence, which is a read to the status register USR followed by an ac
-
cess to the RXR data register.
·
FERR
The FERR flag is the framing error flag. When this read only flag is ²0², it indicates that there¢s
no framing error. When the flag is ²1², it indicates that a framing error has been detected for the
current character. The flag can also be cleared by a software sequence which will involve a read
to the USR status register followed by an access to the RXR data register.
·
NF
The NF flag is the noise flag. When this read only flag is ²0², it indicates a no noise condition.
When the flag is ²1², it indicates that the UART has detected noise on the receiver input. The NF
flag is set during the same cycle as the RXIF flag but will not be set in the case of an overrun.
The NF flag can be cleared by a software sequence which will involve a read to the USR status
register, followed by an access to the RXR data register.
· PERR
The PERR flag is the parity error flag. When this read only flag is ²0², it indicates that a parity er-
ror has not been detected. When the flag is ²1², it indicates that the parity of the received word is
incorrect. This error flag is applicable only if Parity mode (odd or even) is selected. The flag can
also be cleared by a software sequence which involves a read to the USR status register, fol-
lowed by an access to the RXR data register.
Chapter 1 Hardware Structure
69
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