Holtek HT66F20 - Page 199

Rev. 2.50 198 June 22, 2017 Rev. 2.50 199 June 22, 2017
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
I
2
C Bus Read/Write Signal
TheSRWbitintheSIMC1registerdeneswhethertheslavedevicewishestoreaddatafromthe
I
2
CbusorwritedatatotheI
2
Cbus.Theslavedeviceshouldexaminethisbittodetermineifitisto
beatransmitterorareceiver.IftheSRWagis1thenthisindicatesthatthemasterdevicewishesto
readdatafromtheI
2
Cbus,thereforetheslavedevicemustbesetuptosenddatatotheI
2
Cbusasa
transmitter.IftheSRWagis0thenthisindicatesthatthemasterwishestosenddatatotheI
2
Cbus,
thereforetheslavedevicemustbesetuptoreaddatafromtheI
2
Cbusasareceiver.
I
2
C Bus Slave Address Acknowledge Signal
Afterthemasterhastransmittedacallingaddress,anyslavedeviceontheI
2
Cbus,whose
owninternaladdressmatchesthecallingaddress,mustgenerateanacknowledgesignal.The
acknowledgesignalwillinformthemasterthataslavedevicehasaccepteditscallingaddress.Ifno
acknowledgesignalisreceivedbythemasterthenaSTOPsignalmustbetransmittedbythemaster
toendthecommunication.WhentheHAASagishigh,theaddresseshavematchedandtheslave
devicemustchecktheSRWagtodetermineifitistobeatransmitterorareceiver.IftheSRWag
ishigh,theslavedeviceshouldbesetuptobeatransmittersotheHTXbitintheSIMC1register
shouldbesetto"1".IftheSRWagislow,thenthemicrocontrollerslavedeviceshouldbesetupas
areceiverandtheHTXbitintheSIMC1registershouldbesetto"0".
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2
C Bus Data and Acknowledge Signal
Thetransmitteddatais8-bitswideandistransmittedaftertheslavedevicehasacknowledged
receiptofitsslaveaddress.TheorderofserialbittransmissionistheMSBrstandtheLSBlast.
Afterreceiptof8-bitsofdata,thereceivermusttransmitanacknowledgesignal,level0,beforeit
canreceivethenextdatabyte.Iftheslavetransmitterdoesnotreceiveanacknowledgebitsignal
fromthemasterreceiver,thentheslavetransmitterwillreleasetheSDAlinetoallowthemaster
tosendaSTOPsignaltoreleasetheI
2
CBus.ThecorrespondingdatawillbestoredintheSIMD
register.Ifsetupasatransmitter,theslavedevicemustrstwritethedatatobetransmittedintothe
SIMDregister.Ifsetupasareceiver,theslavedevicemustreadthetransmitteddatafromtheSIMD
register.
Whentheslavereceiverreceivesthedatabyte,itmustgenerateanacknowledgebit,knownas
TXAK,onthe9thclock.Theslavedevice,whichissetupasatransmitterwillchecktheRXAKbit
intheSIMC1registertodetermineifitistosendanotherdatabyte,ifnotthenitwillreleasethe
SDAlineandawaitthereceiptofaSTOPsignalfromthemaster.