Holtek HT66F20 - UART Data Transfer Scheme

Rev. 2.50 240 June 22, 2017 Rev. 2.50 241 June 22, 2017
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
Toinitiateadatatransaction,theMCUmasterSPIneedstopullSCStoalowlevelrstandthen
alsopullSCKlow.TheinputdatabitonSDIshouldbestablebeforethenextSCKrisingedge,as
thedevicewilllatchtheSDIstatusonthenextSCKrisingedge.RegardingtheSDOline,theoutput
databitwillbeupdatedontheSCKfallingedge.Themasterneedstoobtainthelinestatusbefore
thenextSCKfallingedge.
Thereare16bitsofdatatransmittedand/orreceivedbytheSPIinterfaceforeachtransaction.Each
transactionconsistsofacommandphaseandadataphase.WhenSCSishigh,theSPIinterfaceis
disabledandSDOwillbesettoahighimpedancestate.
Afteracompletetransactionhasbeenimplemented,whichrequires16SCKclockcycles,themaster
needstosetSCStoahighlevelinpreparationforthenextdatatransaction.
Forwriteoperations,thedevicewillbegintoexecutethecommandonlyafteritreceivesa16-bit
serialdatasequenceandwhentheSCShasbeensethighagainbythemaster.
Forreadoperations,thedevicewillbegintoexecutethecommandonlyafteritreceivesan8-bit
readcommandafterwhichitwillbereadytooutputdata.Ifnecessary,themastercande-assertthe
SCSpintoabortthetransactionatanytimewhichwillcauseanydatatransactionstobeabandoned.
UART Module External Pin Interfacing
Tocommunicatewithanexternalserialinterface,theinternalUARThastwoexternalpinsknownas
TXandRX.TheTXpinistheUARTtransmitterserialdataoutputpinifthecorrespondingcontrol
bitsnamedUARTENinUCR1registerandTXENinUCR2registeraresetto1.Ifthecontrolbit
UARTENorTXENisequaltozero,theTXpinisinthestateofhighimpedance.Similarly,theRX
pinistheUARTreceiverserialdatainputpinifthecorrespondingcontrolbitsnamedUARTENand
RXENinUCR1andUCR2registersaresetto1.IfthecontrolbitUARTENorRXENisequalto
zero,theRXpinisinthestateofhighimpedance.
UART Data Transfer Scheme
ThefollowingblockdiagramshowstheoveralldatatransferstructurearrangementfortheUART.
TheactualdatatobetransmittedfromtheMCUisfirsttransferredtotheTXRregisterbythe
applicationprogram.ThedatawillthenbetransferredtotheTransmitterShiftRegisternamedTSR
fromwhereitwillbeshiftedout,LSBrst,ontotheTXpinataratecontrolledbytheBaudRate
Generator.OnlytheTXRregisterisaccessibletotheapplicationprogram,theTransmitterShift
RegisterisnotmappedintotheDataMemoryareaandisinaccessibletotheapplicationprogram.
DatatobereceivedbytheUARTisacceptedontheexternalRXpin,fromwhereitisshiftedin,
LSBrst,totheReceiverShiftRegisternamedRSRataratecontrolledbytheBaudRateGenerator.
Whentheshiftregisterisfull,thedatawillthenbetransferredfromtheshiftregistertotheinternal
RXRregister,whereitisbufferedandcanbemanipulatedbytheapplicationprogram.Onlythe
RXRregisterisaccessibletotheapplicationprogram,theReceiverShiftRegisterisnotmapped
intotheDataMemoryareaandisinaccessibletotheapplicationprogram.Itshouldbenotedthatthe
actualregisterfordatatransmissionandreception,althoughreferredtointhetext,andinapplication
programs,asseparateTXRandRXRregisters,onlyexistsasasinglesharedregisterphysically.This
sharedregisterknownastheTXR/RXRregisterisusedforbothdatatransmissionanddatareception.