Holtek HT66F20 - Page 253

Rev. 2.50 252 June 22, 2017 Rev. 2.50 253 June 22, 2017
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
• Receivingbreak
AnybreakcharacterreceivedbytheUARTwillbemanagedasaframingerror.Thereceiver
willcountandexpectacertainnumberofbittimesasspeciedbythevaluesprogrammedinto
theBNOandSTOPSbits.Ifthebreakismuchlongerthan13bittimes,thereceptionwillbe
consideredascompleteafterthenumberofbittimesspeciedbyBNOandSTOPS.TheRXIF
bitisset,FERRisset,zerosareloadedintothereceivedataregister,interruptsaregeneratedif
appropriateandtheRIDLEbitisset.Ifalongbreaksignalhasbeendetectedandthereceiverhas
receivedastartbit,thedatabitsandtheinvalidstopbit,whichsetstheFERRag,thereceiver
mustwaitforavalidstopbitbeforelookingforthenextstartbit.Thereceiverwillnotmake
theassumptionthatthebreakconditiononthelineisthenextstartbit.Abreakisregardedas
acharacterthatcontainsonlyzeroswiththeFERRagset.Thebreakcharacterwillbeloaded
intothebufferandnofurtherdatawillbereceiveduntilstopbitsarereceived.Itshouldbenoted
thattheRIDLEreadonlyagwillgohighwhenthestopbitshavenotyetbeenreceived.The
receptionofabreakcharacterontheUARTregisterswillresultinthefollowing:

♦
Theframingerrorag,FERR,willbeset.

♦
Thereceivedataregister,RXR,willbecleared.

♦
TheOERR,NF,PERR,RIDLEorRXIFagswillpossiblybeset.
• Idlestatus
Whenthereceiverisreadingdata,whichmeansitwillbeinbetweenthedetectionofastartbit
andthereadingofastopbit,thereceiverstatusagintheUSRregister,otherwiseknownasthe
RIDLEag,willhaveazerovalue.Inbetweenthereceptionofastopbitandthedetectionof
thenextstartbit,theRIDLEagwillhaveahighvalue,whichindicatesthereceiverisinanidle
condition.
•
Receiverinterrupt
ThereadonlyreceiveinterruptagRXIFintheUSRregisterissetbyanedgegeneratedby
thereceiver.AninterruptisgeneratedifRIE=1,whenawordistransferredfromtheReceive
ShiftRegister,RSR,totheReceiveDataRegister,RXR.Anoverrunerrorcanalsogeneratean
interruptifRIE=1.