HP 9030 CE - Page 68

SYSTEM CLOCK
NOTES
1 MEMORY PROCESSOR BUS INCLUDES:
ADDRESS,
DATA, BUS CONTROL, POWER
AND GROUND, SELF-TEST
MISCELLANEOUS CONTROL
2 MEMORY CONTROLLER
9030/40 Diagrams 9-3
MEMORY PROCESSOR BUS
(MPB)1
3 RAM BOARDS CAN BE 256K,
512K,
OR PAIRS OF 1M BOARDS
LOAD RESISTORS
4 REQUIRED WHEN RAM IS MADE
UP OF SIX OR LESS 1 MEGABYTE
BOARDS; OR ONE CPU, ONE lOP,
AND ONE 512K RAM BOARD.
lOP BUS
CLOCK
BOARD
Boards
CPU
lOP
RAM
LOAD BOARD'
CPU
FINSTRATE
Minimum
1
1
1
* Maximum of 12 boards per stack
lOP
~~~S!"'T=RA--T=E-..J
CPU
Maximum*
3
3
10
Processor Stack Block Diagram