Appendix A. Connector Pin Assignments
IDE Connectors
1
2
40
39
Figure 5. IDE Connector
The IDE connectors are 40-pin, shrouded berg strips located on the system board.
Table 39. Pin Assignments for the IDE Connectors
Pin Signal Name I/O Pin Signal Name I/O
1 Reset O 2 Ground NA
3 D7 I/O 4 D8 I/O
5 D6 I/O 6 D9 I/O
7 D5 I/O 8 D10 I/O
9 D4 I/O 10 D11 I/O
11 D3 I/O 12 D12 I/O
13 D2 I/O 14 D13 I/O
15 D1 I/O 16 D14 I/O
17 D0 I/O 18 D15 I/O
19 Ground NA 20 Key NA
21 DMA REQ NA 22 Ground NA
23 IOW# O 24 Ground NA
25 IOR# O 26 Ground NA
27 IOCHRDY I 28 CSEL O
29 DMA ACK# NA 30 Ground NA
31 IRQ I 32 CS16# I
33 SA1 O 34 No connect I
35 SA0 O 36 SA2 O
37 CS0# O 38 CS1# O
39 Active# I 40 Ground NA
42 Technical Information Manual
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