IBM Personal System/2 50 - RT;CMOS RAM I;O Operations

RT/CMOS
RAM
I/O
Operations
During
I/O
operations
to
the
RT/CMOS
RAM
addresses,
interrupts
should
be
masked
to
prevent
other
interrupt
service
routines
from
changing
the
CMOS
address
register
before
data
is
read
or
written.
After
1/O
operations,
the
RT/CMOS
and
NMI
Mask
register
(hex
0070)
should
be
left
pointing
to
Status
Register
D
(hex
00D).
Warning:
The
operation
following
a
write
to
hex
0070
should
access
hex
0071;
otherwise
intermittent
malfunctions
and
unreliable
operation
of
the
RT/CMOS
RAM
can
occur.
The
following
steps
are
required
to
perform
I/O
operations
to
the
RT/CMOS
RAM
addresses:
1.
Write
the
RT/CMOS
RAM
address
to
the
RT/CMOS
and
NMI
Mask
register
(hex
0070).
2.
Write
the
data
to
address
hex
0071.
Reading
RT/CMOS
RAM
requires
the
following
steps:
1.
Write
the
RT/CMOS
RAM
address
to
the
RT/CMOS
and
NMI
Mask
register
(hex
0070).
2.
Read
the
data
from
address
hex
0071.
3-14
Model
50
System
Board
~
October
1990