ifi Pro iDSD - Technical Details - Buffering and Isolation; Zero Jitter Memory Buffer; Studio Grade DSD1024 Remastering

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Zero Jitter Memory Buffer for all inputs
Data for all inputs is sent to a large 'dynamic' memory buffer, where it is de-jittered to eliminate any transmission of
source jitter to the DAC output. The memory buffer data is then re-clocked by the low-jitter Global Master Timing®
clock, which also drives the X-Core 200 & FPGA engine.
Studio Grade DSD1024 Remastering
While the X-Core 200 is optimal for USB audio, AES/EBU/S/PDIF, MQA, DSD etc. decoding, it is not the best platform
for DSP, digital lters and PCM-to-DSD conversion.
The other half of the digital processing is carried out by the Crysopeia FPGA engine. It handles digital ltering and
PCM-to-DSD remastering up to DSD1024. We believe that FPGA excels in upsampling and digital ltering duties.
On-board hardware upsampling allows us to not only overcome the current DSD512 USB limitation, but also to implement
multiple filters optimized for specific time-domain behavior related to both stages; digital and analogue. This level of
optimization is simply not possible in generic software upconversion (as found in i.e. Foobar 2000).