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Infineon Technologies TC1728 User Manual
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User’s Manual
V1.0 2011-12
Microcontrollers
TC1728
32-Bit Single-Chip Microcontroller
2
Table of Contents
Default Chapter
5
Table of Contents
5
1 Introduction
39
About this Document
39
Related Documentations
39
Text Conventions
39
Reserved, Undefined, and Unimplemented Terminology
41
Register Access Modes
41
Abbreviations and Acronyms
42
System Architecture of the TC1728
45
TC1728 Block Diagram
46
System Features
47
CPU Cores of the TC1728
48
High-Performance 32-Bit CPU
48
High-Performance 32-Bit Peripheral Control Processor
49
On-Chip System Units
50
Flexible Interrupt System
50
System Timer
51
System Control Unit
52
Clock Generation Unit
52
Features of the Watchdog Timer
52
Reset Operation
52
External Interface
53
Development Support
53
2 CPU Subsystem
54
TC1728 Processor Subsystem
54
Central Processing Unit Features
55
CPU Diagram
56
Instruction Fetch Unit
57
Execution Unit
58
General Purpose Register File
59
CPU Implementation-Specific Features
60
Context Save Areas
60
Program Counter Register - PC
60
Interrupt System
61
Trap System
61
Memory Integrity Error Handling
62
Program Side Memories
62
Data Side Memories
64
Tricore 1.3 Compatibility
67
CPU Subsystem Registers
68
CPU Core Special Function Registers (CSFR)
69
Registers
71
CPU General Purpose Registers
76
CPU Memory Protection Registers
79
FPU Registers
85
Registers
86
Memory Integrity Registers
87
Register Descriptions
89
CPU Slave Interface (CPS) Registers
104
Register Descriptions
105
Core Debug Registers
108
Implementation Specific Reset Values
110
CPU Instruction Timing
111
Integer-Pipeline Instructions
112
Simple Arithmetic Instruction Timings
112
Multiply Instruction Timings
116
Multiply Accumulate (MAC) Instruction Timing
117
Control Flow Instruction Timing
118
Load-Store Pipeline Instructions
119
Address Arithmetic Timing
119
Control Flow Instruction Timing
120
Load Instruction Timing
121
Store Instruction Timing
122
Floating Point Pipeline Timing
123
Program Memory Interface (PMI)
124
PMI Features
124
LMB Access Priorities
125
Scratchpad RAM
125
Instruction Cache
126
Program Line Buffer
127
PMI Registers
128
PMI Register Descriptions
129
Data Memory Interface (DMI)
135
DMI Features
135
LMB Access Priorities
136
Local Data RAM (LDRAM)
136
Data Cache
136
Data Line Buffer
137
DMI Trap Generation
138
DMI Registers
140
DMI Register Descriptions
142
3 System Control Unit (SCU)
156
Clock System Overview
157
Clock Generation Unit
159
Overview
159
Oscillator Circuit (OSC)
160
Phase-Locked Loop (PLL) Module
162
ERAY Phase-Locked Loop (PLL_ERAY) Module
170
Clock Control Unit
178
External Clock Output
179
CGU Registers
184
Module Clock Generation
203
Clock Control Register CLC
204
Reset Operation
217
Overview
217
Reset Types
217
Reset Sources Overview
218
Module Reset Behavior
218
General Reset Operation
219
Reset State Machine
220
Reset Counters (RSTCNTA and RSTCNTD)
221
De-Assertion of a Reset
222
Example1
222
Example2
222
Example3
222
Reset Triggers
223
Specific Reset Triggers
223
Configurable Reset Triggers
223
Debug Specific Behavior
223
EEC Reset Specific Behavior
223
Reset Controller Registers
224
Status Registers
224
Configuration Registers
227
External Interface
232
External Service Requests (Esrx)
232
Esrx as Reset Request Trigger
232
Esrx as Reset Output
233
ESR Registers
234
External Request Unit (ERU)
241
Introduction
241
ERU Pin Connections
243
External Request Select Unit (ERS)
243
Event Trigger Logic (ETL)
244
Connecting Matrix
246
Output Gating Unit (OGU)
248
ERU Output Connections
252
External Request Unit Registers
254
Power Supply and Control
270
Basic Operation
270
Enhanced Reset System
274
Power-Up Flow
274
EVR Control Registers
276
Power Management
278
Power Management Overview
278
Power Management Modes
279
Idle Mode
279
Sleep Mode
280
Power Management Control and Status Register, PMCSR
280
Software Boot Support
283
Configuration Done with Start-Up
283
Start-Up Configuration Options
283
Start-Up Registers
284
Start-Up Status Register
284
ECC Error Handling
287
ECC Software Testing Support
287
ECC Registers
288
Watchdog Timer
295
Watchdog Timer Overview
295
Features of the Watchdog Timer
295
The Endinit Function
296
Password Access to WDT_CON0
298
Modify Access to WDT_CON0
299
Access to Endinit-Protected Registers
299
Timer Operation
300
Timer Modes
300
WDT Reset Behavior
302
WDT Operation During Power-Saving Modes
303
Suspend Mode Support
304
Watchdog Timer Registers
304
Watchdog Timer Control Register 0
304
Watchdog Timer Control Register 1
306
Watchdog Timer Status Register
308
Emergency Stop Output Control
311
Emergency Stop Register
312
Interrupt Generation
314
Interrupt Control Registers
315
NMI Trap Generation
325
Trap Control Registers
326
Miscellaneous System Control Register
334
GPTA Input IN1 Control
334
System Control Register
334
Identification Registers
336
SCU Kernel Registers
339
SCU Address Area
345
4 On-Chip System Buses and Bus Bridges
346
What Is New
347
Local Memory Bus
348
Overview
348
Transaction Types
348
Single Transfers
348
Block Transfers
349
Atomic Transfers
349
Address Alignment Rules
349
Reaction of a Busy Slave
349
LMB Basic Operation
350
Local Memory Bus Controller Unit
351
Basic Operation
351
LMB Bus Arbitration
351
LMB Bus Default Master
352
LMB Bus Error Handling
352
LMB Bus Control Unit Registers
353
LMB Bus Control Unit Control Registers
356
Local Memory Bus to FPI Bus Interface (LFI Bridge)
369
Functional Overview
369
LMB to FPI Bridge Control Registers
371
LFI Register Description
372
System Peripheral Bus
374
Overview
374
Bus Transaction Types
376
Reaction of a Busy Slave
376
Address Alignment Rules
377
FPI Bus Basic Operations
377
FPI Bus Control Unit (SBCU)
379
FPI Bus Arbitration
379
Arbitration on the System Peripheral Bus
379
Starvation Prevention
381
FPI Bus Error Handling
381
BCU Debug Support
384
Address Triggers
384
Signal Status Triggers
385
Grant Triggers
386
Combination of Triggers
387
BCU Breakpoint Generation Examples
387
System Bus Control Unit Registers
390
SBCU ID Register Description
392
SBCU Control Registers Descriptions
393
SBCU Error Registers Descriptions
394
SBCU OCDS Registers Descriptions
398
SBCU Service Request Control Register Description
411
On Chip Bus Master TAG Assignments
412
5 Program Memory Unit (PMU)
413
Bootrom
415
Addressing
415
Firmware Program Structure
415
Overlay RAM and Data Acquisition
416
Internal Overlay Memory
416
Online Data Acquisition (OLDA)
416
Access Performance
417
Overlay Memory Control Register
417
Emulation Memory Interface
419
PMU ID Register
420
Tuning Protection
421
Program and Data Flash
422
Introduction
422
Architectural and Operational Overview
426
Sector and
426
Data Flash and EEPROM Emulation
427
Operational Overview
429
Flash Access Control and Performance
436
Functional Description
438
Address Mapping
438
Basic Operating Modes
440
Command Sequence Definitions
440
Functional Command Description
443
Sector, Page and Block Addressing
452
Register Addresses and Access Restrictions
455
Flash Status Definition
458
Flash Configuration Control
465
Flash Identification Register
471
Error Correction and Margin Control
472
Dynamic Error Correction
472
Margin Check Control
473
Read and Write Protection
476
Read Protection
476
Write and OTP Protection
479
Protection Configuration Indication
480
User Configuration Blocks and
486
Interrupt, Error and Operation Control
488
Interrupt Control
488
Trap Control
488
Handling Errors During Operation
489
Handling Errors During Startup
494
Application Hints and Guidelines
496
Power Supply and Reset
499
Flash Power Consumption
499
Flash Sleep Mode
499
Power Supply
499
Reset Control
501
Emergency Programming
505
Data Access Overlay (OVC)
509
Basic Overlay Control
509
Online Data Acquisition (OLDA) and Its Overlay
512
Enable Control of Overlay Blocks
512
Target and Overlay Memories
513
Target Memories
513
Internal Overlay Memory
513
Emulation Overlay Memory
514
External Overlay Memory
514
Change of Overlay Parameters and Overlay Start
514
Block Priority and Access Performance
515
Overlay Control Registers
515
Bootrom Content
530
Startup Software
530
Boot Options Summary
530
Conditions Upon SSW Entry
531
Startup Software Main Flow
532
Entering the Startup Software
533
Initial Handling of the Startup Configuration
533
Basic Device Settings
534
Flash Rampup
534
Rams Handling
534
Select and Prepare Startup Modes
535
Final Chip Settings
537
Ending the SSW and Starting the User Code
539
Specific SSW Features
539
Header Check in Alternate Boot Modes
539
Startup Errors Handling
541
Bootstrap Loaders
542
Common Procedures for All Bootloaders
542
ASC Bootstrap Loader
543
CAN Bootstrap Loader
543
Influencing the Next SSW-Execution
545
8 Memory Maps
546
What Is New
547
How to Read the Address Maps
548
Contents of the Segments
550
Address Map of the FPI Bus System
552
Segments 0 to 14
552
Segment 15
557
Address Map of the Local Memory Bus (LMB)
564
Memory Module Access Restrictions
569
Side Effects from Modules to LDRAM
570
9 General Purpose I/O Ports and Peripheral I/O Lines (Ports)
571
Basic Port Operation
571
Description Scheme for the Port IO Functions
574
Port Register Description
576
Port Input/Output Control Registers
580
Pad Driver Mode Register
584
Pin Function Decision Control Register
588
Port Output Register
589
Port Output Modification Register
590
Emergency Stop Register
592
Port Input Register
593
Port 0
595
Port 0 Configuration
595
Port 0 Function Table
595
Port 0 Registers
600
Port 1
601
Port 1 Configuration
601
Port 1 Function Table
602
Port 1 Registers
607
Port 1 Emergency Stop Register
607
Port 2
608
Port 2 Configuration
608
Port 2 Function Table
608
Port 2 Registers
613
Port 2 Output Register
613
Port 2 Output Modification Register
613
Port 2 Input/Output Control Register 12
614
Port 2 Input Register
614
Port 2 Pad Driver Mode 1 Register
615
Port 2 Emergency Stop Register
615
Port 3
617
Port 3 Configuration
617
Port 3 Function Table
617
Port 3 Registers
622
Port 3 Emergency Stop Register
622
Port 4
623
Port 4 Configuration
623
Port 4 Function Table
623
Port 4 Registers
624
Port 4 Output Register
625
Port 4 Output Modification Register
625
Port 4 Input/Output Control Register X (X = 4, 8 and 12)
625
Port 4 Input Register
625
Port 4 Pad Driver Mode 0 Register
626
Port 4 Emergency Stop Register
626
Port 5
627
Port 5 Configuration
627
Port 5 Function Table
627
Port 5 Registers
632
Port 6
633
Port 6 Configuration
633
Port 6 Function Table
634
Port 6 Registers
635
Port 6 Output Register
635
Port 6 Output Modification Register
635
Port 6 Input Register
635
Port 6 Pad Driver Mode 0 Register
636
Port 6 Emergency Stop Register
637
Port 8
638
Port 8 Configuration
638
Port 8 Function Table
639
Port 8 Register
643
Port 8 Output Register
643
Port 8 Output Modification Register
643
Port 8 Input/Output Control Register 12
644
Port 8 Input Register
644
Port 8 Pad Driver Mode 1 Register
645
Port 9
646
Port 9 Configuration
646
Port 9 Function Table
647
Port 9 Registers
650
Port 9 Output Register
650
Port 9 Output Modification Register
650
Port 9 Input/Output Control Register 8
651
Port 9 Input Register
651
Port 9 Pad Driver Mode 1 Register
652
Port 9 Emergency Stop Register
652
Port 10
653
Port 10 Configuration
653
Port 10 Function Table
653
Port 10 Registers
655
Port 10 Output Register
655
Port 10 Output Modification Register
655
Port 10 Input Register
655
Port 10 Pad Driver Mode 0 Register
656
Port 11
657
Port 11 Configuration
657
Port 11 Function Table
658
Port 11 Registers
660
Port 11 Input/Output Control Registers
661
Port 11 Pin Function Decision Control Register
664
Port 12
667
Port 12 Configuration
667
Port 12 Function Table
668
Port 12 Registers
669
Port 12 Input/Output Control Registers
670
Port 12 Pin Function Decision Control Register
671
10 Peripheral Control Processor (PCP)
673
PCP Feature/Enhancement History List
673
Switchable Core Clock Ratio
674
Peripheral Control Processor Overview
674
High Integrity Operation
674
PCP Architecture
675
PCP Processor
676
PCP Code Memory
677
CMEM Protection
677
PCP Parameter RAM
677
PRAM Protection
678
FPI Bus Interface
678
PCP Interrupt Control Unit and Service Request Nodes
678
PCP Programming Model
680
General Purpose Register Set of the PCP
680
Register R0
681
Registers R1, R2, and R3
681
Registers R4 and R5
681
Register R6
682
Register R7
683
Contexts and Context Models
685
Context Models
685
Context Save Area
688
Context Restore Operation for CR6 and CR7
691
Context Save Operation for CR6 and CR7
695
Initialization of the Contexts
698
Context Save Optimization
698
Channel Programs
699
Channel Restart Mode
699
Channel Resume Mode
700
PCP Operation
702
PCP Initialization
702
Channel Invocation and Context Restore Operation
702
Channel Exit and Context Save Operation
703
Normal Exit
703
Error Condition Channel Exit
704
Debug Exit
705
PCP Interrupt Operation
706
Issuing Service Requests to CPU or PCP
707
PCP Interrupt Control Unit
707
PCP Service Request Nodes
707
Issuing PCP Service Requests
708
Service Request on EXIT Instruction
709
Service Request on Suspension of Interrupt
709
Service Request on Error
710
Queue Full Operation
710
PRAM Protection
711
Protection of PRAM against FPI Writes
713
Protection of PRAM against Internally Generated PRAM Writes
713
Context Save Region Protection
713
Protected Channel PRAM Protection
714
FPI Interface
714
Operation as an FPI Master
714
Operation as an FPI Slave
715
PCP Error Handling
716
PRAM Protection Violation
716
Enforced PRAM Partitioning
716
Protected Channel PRAM
717
FPI Write Window Violation
717
Channel Watchdog
717
Invalid Opcode
717
Instruction Address Error
718
Software In-System Test Support
718
Memory Integrity Error Detection and Correction
719
Definitions
720
Architectural Extensions - Registers
720
Memory Integrity Error Control
720
Instruction Set Overview
722
DMA Primitives
722
Load and Store
723
Arithmetic and Logical Instructions
724
Bit Manipulation
726
Flow Control
726
Addressing Modes
727
FPI Bus Addressing
727
PRAM Addressing
728
Bit Addressing
728
Flow Control Destination Addressing
728
FPI Interface
730
Access to the PCP Control Registers from the FPI Bus
730
PCP Control Register Protection
730
Access to the PRAM from the FPI Bus
731
Access to the CMEM from the FPI Bus
731
Debugging the PCP
733
PCP Registers
735
PCP Registers Address Space
739
Registers
740
PCP Clock Control Register, PCP_CLC
740
PCP Module Identification Register, PCP_ID
741
PCP Control and Status Register, PCP_CS
742
PCP Error/Debug Status Register, PCP_ES
744
PCP Interrupt Control Register, PCP_ICR
746
PCP Interrupt Threshold Register, PCP_ITR
749
PCP Interrupt Configuration Register, PCP_ICON
750
PCP Stall Status Register, PCP_SSR
752
SIST Mode Access Control Register, PCP_SMACON
754
Memory Integrity Error Control Register, PCP_MIECON
755
Memory Integrity Error Control 2 Register, PCP_MIECON2
756
Memory Integrity Error Status Register for PRAM, PCP_MIESTATP
757
Memory Integrity Error Status Register for CMEM, PCP_MIESTATC
758
Register Protection Register, PCP_RPROT
759
CMEM Protection Register, PCP_CPROT
760
PRAM Protection Register, PCP_PPROT
761
FPI Write Window Register, PCP_FWWIN
765
PCP Service Request Control Registers M, PCP_SRC[1:0]
766
PCP Service Request Control Registers M, PCP_SRC[3:2]
768
PCP Service Request Control Registers M, PCP_SRC[8:4]
769
PCP Service Request Control Registers M, PCP_SRC[11:9]
770
PCP Instruction Set Details
772
Instruction Codes and Fields
772
Conditional Codes
773
Instruction Fields
774
Counter Operation for COPY Instruction
777
Counter Operation for BCOPY Instruction
778
Divide and Multiply Instructions
779
ADD, 32-Bit Addition
780
AND, 32-Bit Logical and
781
BCOPY, DMA Operation
782
CHKB, Check Bit
783
CLR, Clear Bit
783
COMP, 32-Bit Compare
784
COPY, DMA Instruction
785
DEBUG, Debug Instruction
786
DINIT, Divide Initialization
787
DSTEP, Divide Instruction
788
EXIT, Exit Instruction
789
INB, Insert Bit
790
JC, Jump Conditionally
791
JL, Jump Long Unconditional
792
LD, Load
792
LDL, Load 16-Bit Value
794
MINIT, Multiply Initialization
794
MOV, Move Register to Register
795
Multiply Instructions
796
NEG, Negate
797
NOP, no Operation
797
NOT, Logical NOT
797
OR, Logical or
798
PRAM Bit Operations
799
PRI, Prioritize
800
RL, Rotate Left
801
RR, Rotate Right
801
SET, Set Bit
802
SHL, Shift Left
802
SHR, Shift Right
803
ST, Store
804
SUB, 32-Bit Subtract
805
XCH, Exchange
806
XOR, 32-Bit Logical Exclusive or
807
Flag Updates of Instructions
808
Instruction Timing
809
Instruction Encoding
813
Programming of the PCP
819
Initial PC of a Channel Program
819
Channel Entry Table
819
Channel Resume
820
Channel Management for Small and Minimum Contexts
821
Unused Registers as Global's or Constants
821
Dispatch of Low Priority Tasks
822
Code Reuse Across Channels (Call and Return)
822
Case-Like Code Switches (Computed Go-To)
823
Simple DMA Operation
823
COPY Instruction
823
BCOPY Instruction (Burst Copy)
824
PCP Programming Notes and Tips
825
Notes on PCP Configuration
825
General Purpose Register Use
825
Use of Channel Interruption
827
Dynamic Interrupt Masking
827
Control of Channel Priority (CPPN)
827
Implementing Divide Algorithms
828
Implementing Multiply Algorithms
829
Implementation of the PCP in the TC1728
831
PCP Memories
831
BCOPY Instruction
831
PCP Reset Operation
832
11 Direct Memory Access Controller (DMA)
833
What Is New
833
DMA Controller Kernel Description
835
Features
836
Definition of Terms
837
DMA Principles
838
DMA Channel Functionality
839
Shadowed Source or Destination Address
839
DMA Channel Request Control
843
DMA Channel Operation Modes
844
Error Conditions
848
Channel Reset Operation
849
Transfer Count and Move Count
850
Circular Buffer
852
Transaction Control Engine
853
Bus Switch, Bus Switch Priorities
854
DMA Module Priorities on on Chip Busses (FPI Bus, LMB Bus)
856
DMA Module: on Chip Bus Access Rights, RMW Support
857
DMA Module on Chip Bus Master Interfaces
857
DMA Module Bridge Functionality
859
On-Chip Debug Capabilities
860
Hard-Suspend Mode
860
Soft-Suspend Mode
860
Break Signal Generation
861
Interrupts
863
Channel Interrupts
863
Transaction Lost Interrupt
865
Move Engine Interrupts
866
Wrap Buffer Interrupts
868
Interrupt Request Compressor
869
Pattern Detection
870
Pattern Compare Logic
872
Pattern Detection for 8-Bit Data Width
873
Pattern Detection for 16-Bit Data Width
874
Pattern Detection for 32-Bit Data Width
876
Access Protection
877
DMA Module Registers
880
System Registers
886
General Control/Status Registers
892
Move Engine Registers
911
Channel Control/Status Registers
918
Channel Address Registers
930
DMA Module Implementation
933
DMA Request Wiring Matrix
934
Access Protection Assignment
944
Implementation-Specific DMA Registers
952
Clock Control Register
954
DMA Interrupt Registers
955
MLI Interrupt Registers
956
Address Map
957
Memory Checker Module
958
Functional Description
958
Ethernet CRC-32 Endianness
959
Memory Checker Module Registers
960
Memory Checker Module Control Registers
961
12 Flexible CRC Engine (FCE)
966
Related Documentation
967
FCE Features
968
Operational Overview
969
FCE Functional Description
971
Interfaces of the FCE Module
978
FCE Module Registers
979
System Registers
982
CRC Kernel Control/Status Registers
986
Programming Guide
993
Properties of CRC Code
996
Revision History
997
13 Interrupt System
998
Overview
998
Service Request Nodes
1000
Service Request Control Registers
1000
General Service Request Control Register Format
1000
Request Set and Clear Bits (SETR, CLRR)
1002
Enable Bit (SRE)
1002
Service Request Flag (SRR)
1002
Type-Of-Service Control (TOS)
1003
Service Request Priority Number (SRPN)
1003
Interrupt Control Units
1005
Interrupt Control Unit (ICU)
1005
ICU Interrupt Control Register (ICR)
1005
Operation of the Interrupt Control Unit (ICU)
1007
PCP Interrupt Control Unit (PICU)
1008
Arbitration Process
1009
Controlling the Number of Arbitration Cycles
1009
Controlling the Duration of Arbitration Cycles
1010
Entering an Interrupt Service Routine
1010
Exiting an Interrupt Service Routine
1011
Interrupt Vector Table
1012
Usage of the TC1728 Interrupt System
1015
Spanning Interrupt Service Routines Across Vector Entries
1015
Configuring Ordinary Interrupt Service Routines
1016
Interrupt Priority Groups
1016
Splitting Interrupt Service Across Different Priority Levels
1017
Using Different Priorities for the same Interrupt Source
1018
Interrupt Priority 1
1019
Software-Initiated Interrupts
1019
External Interrupts
1019
Service Request Node Table
1020
14 System Timer (STM)
1023
Overview
1023
Operation
1023
Resolution and Ranges
1026
Compare Register Operation
1027
Compare Match Interrupt Control
1028
STM Registers
1029
Clock Control Register
1031
Timer/Capture Registers
1033
Compare Registers
1036
Interrupt Registers
1039
STM Module Implementation
1043
On-Chip Service Request Connections
1043
STM Address Map
1043
15 Bus Monitor Unit (BMU)
1045
Related Documentation
1046
BMU Features
1047
Operational Overview
1048
Microcontroller Monitoring Framework
1048
Bus Monitor Unit Overview
1050
BMU Functional Description
1052
BMU Microarchitecture
1052
Handling of FPI Corner Cases
1055
Bus Transaction Table
1056
Write Operation and Fifo Structure
1058
Read Operation and Fifo Structure
1059
Fullness Monitoring
1060
Error Correction Code (ECC)
1062
Usage in Non Safety Applications
1064
BMU Interrupts
1065
Peripheral Monitoring Selection
1066
Interfaces of the BMU Module
1068
BMU Module Registers
1070
System Registers Description
1073
BMU Control/Status Registers
1076
BMU: Bus Logging Configuration Registers
1079
BMU: Fifo Monitoring Registers
1086
BMU: SIST Mode Access Control Register
1089
Interrupt System Registers
1092
Revision History
1094
16 On-Chip Debug Support (OCDS)
1097
Overview
1097
OCDS Level 1
1101
Tricore CPU OCDS Level 1
1102
Basic Concept
1102
Debug Event Generation
1103
Debug Actions
1104
Tricore OCDS Registers
1104
PCP OCDS Level 1
1105
SBCU OCDS Level 1
1105
DMA OCDS Level 1
1105
Debug Interface (Cerberus)
1106
RW Mode
1106
Communication Mode
1107
Triggered Transfers
1107
Multi Core Break Switch
1107
JTAG Interface
1109
Device Access Port (DAP)
1109
DAP Telegram Format
1109
DAP Telegram Catalog
1109
Cerberus and JTAG Registers
1110
17 Asynchronous/Synchronous Serial Interface (ASC)
1113
ASC Kernel Description
1113
Overview
1114
General Operation
1115
Asynchronous Operation
1116
Asynchronous Data Frames
1117
Asynchronous Transmission
1119
Asynchronous Reception
1119
RXD/TXD Data Path Selection in Asynchronous Modes
1120
Synchronous Operation
1121
Synchronous Transmission
1122
Synchronous Reception
1122
Synchronous Timing
1123
Baud Rate Generation
1124
Baud Rates in Asynchronous Mode
1125
Baud Rates in Synchronous Mode
1129
Hardware Error Detection Capabilities
1131
Interrupts
1131
ASC Kernel Registers
1133
Control Registers
1134
Data Registers
1142
ASC0/ASC1 Module Implementation
1144
Interfaces of the ASC Modules
1144
ASC0/ASC1 Module Related External Registers
1146
Clock Control Register
1147
Peripheral Input Select Register
1149
Port Control Registers
1151
Interrupt Control Registers
1153
DMA Requests
1154
Address Map
1155
18 Synchronous Serial Interface (SSC)
1158
SSC Kernel Description
1158
Overview
1159
General Operation
1160
Operating Mode Selection
1162
Full-Duplex Operation
1163
Half-Duplex Operation
1166
Continuous Transfers
1167
Parity Mode
1168
Port Control
1169
Baud Rate Generation
1171
Slave Select Input Operation
1173
Slave Select Output Generation Unit
1174
Error Detection Mechanisms
1177
Queued SSC Mode
1181
SSC Kernel Registers
1184
Module Identification Register
1185
Control Registers
1186
Data Registers
1199
SSC0/SSC1/SSC2/SSC3 Module Implementation
1200
Module Identification Registers
1200
Interfaces of the SSC Modules
1200
On-Chip Connections
1203
SSC0/SSC1/SSC2/SSC3 Module Related External Registers
1203
Clock Control
1205
Port Control
1210
Interrupt Control Registers
1215
Address Map of the SSC Modules
1216
19 Micro Second Channel (MSC)
1220
MSC Kernel Description
1222
Overview
1222
Downstream Channel
1224
Frame Formats and Definitions
1225
Shift Register Operation
1231
Transmission Modes
1233
Downstream Counter and Enable Signals
1238
Baud Rate
1239
Abort of Frames
1239
Upstream Channel
1240
Data Frames
1241
Parity Checking
1241
Data Reception
1242
Baud Rate
1244
Spike Filter
1245
I/O Control
1246
Downstream Channel Output Control
1246
Upstream Channel
1249
MSC Interrupts
1250
Data Frame Interrupt
1251
Command Frame Interrupt
1251
Time Frame Finished Interrupt
1252
Receive Data Interrupt
1253
Interrupt Request Compressor
1254
MSC Kernel Registers
1255
Module Identification Register
1257
Status and Control Registers
1258
Data Registers
1278
MSC Module Implementation
1281
Interface Connections of the MSC Module
1281
MSC0 Module-Related External Registers
1283
Clock Control
1284
Clock Control Register
1286
Fractional Divider Register
1287
Port Control
1288
Input/Output Function Selection
1288
On-Chip Connections
1290
EMGSTOPMSC Signal (from SCU)
1290
DMA Controller Service Requests
1290
Interrupt Control Registers
1291
MSC0 Address Map
1292
20 Controller Area Network Controller (Multican)
1294
CAN Basics
1295
Addressing and Bus Arbitration
1295
CAN Frame Formats
1296
Data Frames
1296
Remote Frames
1298
Error Frames
1300
The Nominal Bit Time
1301
Error Detection and Error Handling
1302
Overview
1304
Multican Module
1305
Multican Kernel Functional Description
1307
Module Structure
1307
Clock Control
1310
Port Input Control
1312
Suspend Mode
1312
CAN Node Control
1314
Bit Timing Unit
1315
Bitstream Processor
1316
Error Handling Unit
1317
CAN Frame Counter
1318
CAN Node Interrupts
1318
Message Object List Structure
1320
Basics
1320
List of Unallocated Elements
1321
Connection to the CAN Nodes
1321
List Command Panel
1322
CAN Node Analysis Features
1325
Analyze Mode
1325
Loop-Back Mode
1325
Bit Timing Analysis
1326
Message Acceptance Filtering
1328
Receive Acceptance Filtering
1328
Transmit Acceptance Filtering
1329
Message Postprocessing
1331
Message Object Interrupts
1331
Pending Messages
1333
Message Object Data Handling
1335
Frame Reception
1335
Frame Transmission
1338
Message Object Functionality
1341
Standard Message Object
1341
Single Data Transfer Mode
1341
Single Transmit Trial
1341
Message Object FIFO Structure
1342
Receive FIFO
1344
Transmit FIFO
1345
Gateway Mode
1346
Foreign Remote Requests
1348
Multican Kernel Registers
1349
Global Module Registers
1352
CAN Node Registers
1367
Message Object Registers
1385
Multican Module Implementation
1406
Interfaces of the Multican Module
1406
Multican Module External Registers
1407
Module Clock Generation
1408
Clock Selection
1408
Fractional Divider
1408
Port and I/O Line Control
1412
Input/Output Function Selection in Ports
1412
Node Receive Input Selection
1412
External CAN Time Trigger Inputs
1414
DMA Request Outputs
1414
Connectons to GPTA0 Inputs
1414
Connectons to CAPCOM6 Inputs
1415
Interrupt Control
1416
CAN Service Request Control Register
1418
Multican Module Register Address Map
1419
21 Flexray™ Protocol Controller (E-Ray)
1421
E-Ray Kernel Description
1421
Overview
1422
Definitions
1423
Block Diagram
1423
Programmer's Model
1426
Register Map
1426
E-Ray Kernel Registers
1428
Customer Registers
1428
Special Registers
1428
Service Request Registers
1428
Communication Controller Control Registers
1429
Communication Controller Status Registers
1430
Message Buffer Control Registers
1431
Message Buffer Status Registers
1431
Identification Registers
1434
Input Buffer
1434
Service Request Registers
1462
Output Buffer
1600
Functional Description
1617
Dynamic Segment
1618
Communication Modes
1620
Synchronization Process
1621
External Clock Synchronization
1622
Error Handling
1623
Passive to Active Counter
1624
Communication Controller States
1626
DEFAULT_CONFIG State
1628
Monitor_Mode
1629
READY State
1630
STARTUP State
1635
Startup Timeouts
1638
Path of Leading Coldstart Node (Initiating Coldstart)
1639
NORMAL_ACTIVE State
1641
HALT State
1642
Network Management
1643
Frame ID Filtering
1644
Cycle Counter Filtering
1645
FIFO Filtering
1646
Transmit Process
1647
Frame Transmission
1648
NULL Frame Transmission
1649
Receive Process
1650
NULL Frame Reception
1651
Configuration of the FIFO
1652
Access to the FIFO
1653
Data Transfers between IBF / OBF and Message RAM
1658
Minimum F CLC_ERAY
1666
Flexray™ Protocol Controller Access to Message RAM
1668
Message RAM
1669
Header Partition
1671
Data Partition
1674
ECC Check
1675
Host Handling of Errors
1678
Module Service Request
1680
Restrictions
1683
E-Ray Module Implementation
1685
Port Control and Connections
1686
On-Chip Connections
1688
E-Ray Connections with the External Request Unit of SCU
1689
Clock Control Register
1690
Interrupt Registers
1692
E-Ray Access Delay
1703
Micro Link Interface (MLI)
1705
Functional Description
1706
Naming Conventions
1708
MLI Communication Principles
1710
MLI Frame Structure
1714
General Frame Layout
1715
Copy Base Address Frame
1716
Write Offset and Data Frame
1717
Optimized Write Frame
1718
Discrete Read Frame
1719
Optimized Read Frame
1720
Command Frame
1721
Answer Frame
1722
Handshake Description
1723
Handshake Signals
1725
Ready Delay Time
1726
Non-Acknowledge Error
1727
Signal Timing
1728
Parity Generation
1730
Module Kernel Description
1731
Copy Base Address Frame
1732
Write/Data Frames
1734
Read Frames
1738
Answer Frame
1743
Command Frame
1745
General MLI Features
1748
Non-Acknowledge Error
1751
Automatic Data Mode
1752
Memory Access Protection
1753
Transmit Priority
1754
Interface Description
1755
Transmitter I/O Line Control
1757
Connecting Several MLI Modules
1759
MLI Service Request Generation
1761
Transmitter Events
1763
Parity/Time-Out Error Event
1764
Command Frame Sent Events
1765
Receiver Events
1766
Memory Access Protection/Parity Error Event
1767
Normal Frame Received/Move Engine Terminated Event
1768
Interrupt Command Frame Event
1769
Command Frame Received Event
1770
Baud Rate Generation
1771
Automatic Register Overwrite
1772
Operating the MLI
1773
Connection Setup
1774
Local Transmitter and Pipe Setup
1775
Remote Transmitter and Local Receiver Setup
1776
Delay Adjustment
1777
Connection to DMA Mechanism
1779
MLI Kernel Registers
1781
General Module Registers
1783
General Status/Control Registers
1787
Access Protection Registers
1794
Transmitter Control/Status Registers
1796
Transmitter Pipe X Address Offset Register
1807
Transmitter Interrupt Registers
1811
Receiver Control/Status Registers
1817
Receiver Address/Data Registers
1821
Receiver Interrupt Registers
1824
Implementation of the MLI0 in TC1728
1831
MLI Module External Registers
1833
Module Clock Generation
1834
Port Control and Connections
1836
On-Chip Connections
1838
Break Signals
1839
MLI0 Address Map
1840
General Purpose Timer Array (GPTA ® V5)
1844
Functionality of GPTA0
1848
GPTA0 Kernel Description
1851
GTPA Units
1852
Clock Generation Cells
1853
Filter and Prescaler Cell (FPC)
1855
Phase Discrimination Logic (PDL)
1864
Duty Cycle Measurement Cell (DCM)
1869
Digital Phase Locked Loop Cell (PLL)
1873
Clock Distribution Cell (CDC)
1878
Signal Generation Cells
1881
Global Timer Cell (GTC)
1898
Local Timer Cell (LTC00 to LTC62)
1910
Local Timer Cell LTC63
1922
Coherent Update
1928
Input/Output Line Sharing Block (IOLS)
1941
FPC Input Line Selection
1945
GTC and LTC Output Multiplexer Selection
1946
On-Chip Trigger and Gating Output Multiplexer Selection
1951
GTC Input Multiplexer Selection
1954
LTC Input Multiplexer Selection
1959
Multiplexer Register Array Programming
1964
Interrupt Sharing Block (IS)
1966
FPC Algorithm
1969
PDL-Algorithm
1974
DCM-Algorithm
1978
PLL-Algorithm
1981
GT-Algorithm
1983
GTC-Algorithm
1984
LTC-Algorithm for Cells 0 to 62
1989
LTC Algorithm for Cell 63
1997
GPTA0 Kernel Registers
2003
GPTA ® V5 Identification Register
2009
FPC Registers
2010
Phase Discriminator Registers
2014
Duty Cycle Measurement Registers
2016
Digital Phase Locked Loop Registers
2019
Global Timer Registers
2023
Clock Bus Register
2025
Global Timer Cell Registers
2027
Local Timer Cell Registers
2032
Multiplexer Control Registers
2046
Service Request Registers
2062
Interconnections of GPTA0 Units
2072
Port Control and Connections
2074
Input/Output Function Selection
2076
On-Chip Connections
2080
Connections to SCU, Multican, FADC, DMA, Ports
2083
Module Clock Generation
2085
Clock Control Registers
2088
Fractional Divider Register
2089
Limits of Cascading Gtcs and Ltcs
2093
Interrupt Registers
2094
Capture/Compare Unit 6 (CCU6)
2096
Feature Set Overview
2097
Block Diagram
2098
CCU6 Kernel Registers
2099
Operating Timer T12
2105
T12 Overview
2106
T12 Counting Scheme
2108
Edge-Aligned / Center-Aligned Mode
2109
Single-Shot Mode
2111
T12 Compare Mode
2112
Channel State Bits
2113
Hysteresis-Like Control Mode
2118
Compare Mode Output Path
2119
State Selection
2121
Output Modulation and Level Selection
2122
T12 Capture Modes
2124
T12 Shadow Register Transfer
2128
Timer T12 Operating Mode Selection
2129
T12 Related Registers
2130
Period Register
2131
Capture/Compare Registers
2132
Capture/Compare Shadow Registers
2133
Dead-Time Control Register
2134
Capture/Compare Control Registers
2136
T12 Mode Control Register
2140
Timer Control Registers
2141
Operating Timer T13
2150
T13 Counting Scheme
2153
T13 Counting
2154
Single-Shot Mode
2155
Synchronization to T12
2156
T13 Compare Mode
2158
Compare Mode Output Path
2160
T13 Shadow Register Transfer
2161
T13 Related Registers
2163
Period Register
2164
Compare Register
2165
Compare Shadow Register
2166
Synchronous Start Feature
2167
Trap Handling
2168
Multi-Channel Mode
2170
Hall Sensor Mode
2172
Hall Pattern Evaluation
2173
Hall Pattern Compare Logic
2175
Hall Mode Flags
2176
Hall Mode for Brushless DC-Motor Control
2178
Modulation Control Registers
2180
Trap Control Register
2182
Passive State Level Register
2185
Multi-Channel Mode Registers
2186
Interrupt Handling
2193
Interrupt Registers
2195
Interrupt Status Set Register
2198
Status Reset Register
2200
Interrupt Enable Register
2202
Interrupt Node Pointer Register
2204
Service Request Control Registers
2207
General Module Operation
2208
Input Selection
2211
Input Monitoring
2212
General Registers
2213
Port Input Select Registers
2214
Kernel State Configuration Register
2219
Kernel State Sensitivity Control Register
2222
Module Configuration Register
2223
Input Monitoring Register
2225
Lost Indicator Register
2228
Implementation
2230
Module Registers
2231
Module Output Select
2233
Synchronous Start
2234
Digital Connections
2235
Connections of CCU61
2240
General Purpose Timer Units (GPT12)
2245
Timer Block GPT1
2246
GPT1 Core Timer T3 Control
2248
GPT1 Core Timer T3 Operating Modes
2252
GPT1 Auxiliary Timers T2/T4 Control
2259
GPT1 Auxiliary Timers T2/T4 Operating Modes
2265
GPT1 Clock Signal Control
2275
GPT1 Timer Registers
2278
Interrupt Control for GPT1 Timers
2280
Timer Block GPT2
2282
GPT2 Core Timer T6 Control
2284
GPT2 Core Timer T6 Operating Modes
2288
GPT2 Auxiliary Timer T5 Control
2291
GPT2 Auxiliary Timer T5 Operating Modes
2294
GPT2 Register CAPREL Operating Modes
2299
GPT2 Clock Signal Control
2305
GPT2 Timer Registers
2308
Interrupt Control for GPT2 Timers and CAPREL
2310
Miscellaneous Registers
2312
GPT12 Kernel Register Overview
2317
Implementation of the GPT12 Modules
2319
Analog to Digital Converter
2323
ADC Block Diagram
2324
Feature Set
2325
Abbreviations
2326
ADC Kernel Overview
2327
Conversion Request Unit
2329
Conversion Result Unit
2331
Interrupt Structure
2332
Electrical Models
2333
Reference Path
2334
Transfer Characteristics and Error Definitions
2336
Operating the ADC
2337
Register Overview
2338
Mode Control
2344
Module Activation and Power Saving Modes
2346
Clocking Scheme
2347
ADC Module Registers
2348
Kernel State Configuration Register
2349
Service Request Control Registers
2351
Supply Level Control Register
2352
General ADC Kernel Registers
2353
Module Identification Register
2356
Interrupt Activation Register
2357
Global Control
2358
Global Configuration
2361
Global Status
2363
Request Source Arbiter
2366
Request Source Priority
2367
Conversion Start Modes
2368
Arbiter Registers
2371
Request Source Priority Register
2372
Scan Request Source Handling
2374
Scan Sequence Operation
2375
Request Source Event and Interrupt
2376
Scan Request Source Registers
2378
Conversion Request Pending Registers
2380
Conversion Request Mode Registers
2382
Sequential Request Source Handling
2385
Overview
2386
Sequential Source Operation
2387
Request Source Event and Interrupt
2388
Sequential Source Registers
2390
Queue Status Registers
2393
Queue 0 Registers
2395
Queue Backup Registers
2397
Queue Input Registers
2399
Channel-Related Functions
2401
Reference Selection
2402
Limit Checking
2403
Channel Event Interrupts
2405
Channel-Related Registers
2406
Input Class Registers
2409
Alias Register
2410
Limit Check Boundary Registers
2411
Channel Flag Register
2412
Channel Flag Clear Register
2413
Channel Event Node Pointer Registers
2414
Conversion Result Handling
2417
Wait-For-Read Mode
2419
Result Event Interrupts
2420
Result FIFO Buffer
2421
Data Reduction Filter
2423
Conversion Result-Related Registers
2425
Result Registers 1 to 15
2428
Valid Flag Register
2431
Result Control Registers
2432
Event Flag Register
2434
Event Flag Clear Register
2436
Event Node Pointer Registers
2437
Multiplexer Test Support
2440
External Multiplexer Control
2441
Synchronized Conversions for Parallel Sampling
2444
Equidistant Sampling
2447
Access Protection
2449
Broken Wire Detection
2450
Additional Feature Registers
2452
External Multiplexer Control
2453
Synchronization Control Register
2457
Broken Wire Detection Enable Register
2459
Broken Wire Detection Configuration Register
2460
Implementation
2461
ADC Module Connections
2462
ADC0 Connections
2463
ADC1 Connections
2469
Service Request Connections
2476
Kernel Synchronization
2477
Fast Analog to Digital Converter (FADC)
2478
FADC Short Description
2479
FADC Kernel Description
2482
Result Representation
2484
Channel Triggers
2485
Channel Timer
2488
Conversion Control
2489
Suspend Mode Behavior
2490
Alias Feature
2491
Data Reduction Unit
2492
Filter Block Structure
2493
Filter Concatenation
2494
Width of Result Registers
2496
Neighbor Channel Trigger
2497
Calibration
2498
Offset Calibration
2499
Interrupt Generation
2500
FADC Register Description
2503
System Registers
2506
Fractional Divider Register
2507
Module Identification Register
2509
Service Request Control Registers
2510
Global Registers
2511
Flag Modification Register
2513
Neighbor Channel Trigger Register
2515
Global Control Register
2516
Alias Register
2519
Channel Registers
2520
Analog Control Registers
2524
Conversion Result Registers
2526
Filter Registers
2527
Current Result Registers
2530
Intermediate Result Registers
2532
Final Result Registers
2533
Implementation of FADC
2535
Interfaces of the FADC Module
2536
FADC Connections
2537
Service Request Connections
2538
Clock Control
2540
User's Manual L-29 V1.0
2569
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Infineon Technologies TC1728 Specifications
General
Brand
Infineon Technologies
Model
TC1728
Category
Microcontrollers
Language
English
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