Infineon Technologies TC1784

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User´s Manual

V1.1 2011-05

Microcontrollers

TC1784

32-Bit Single-Chip Microcontroller

Main Page

Default Chapter7
- Table of Contents7
1 Introduction40
- About this Document40
- Related Documentations40
- Text Conventions40
- Reserved, Undefined, and Unimplemented Terminology42
- Register Access Modes42
- Abbreviations and Acronyms43
- System Architecture of the TC178446
- TC1784 Block Diagram47
- System Features48
- CPU Cores of the TC178449
- High-Performance 32-Bit CPU49
- High-Performance 32-Bit Peripheral Control Processor50
- On-Chip System Units51
- Flexible Interrupt System51
- Direct Memory Access Controller51
- System Timer52
- System Control Unit55
- Clock Generation Unit55
- Features of the Watchdog Timer55
- Reset Operation55
- External Interface56
- Die Temperature Measurement56
- General Purpose I/O Ports and Peripheral I/O Lines56
- Program Memory Unit (PMU)57
- Boot ROM58
- Overlay RAM and Data Acquisition58
- Emulation Memory Interface58
- Tuning Protection58
- Program and Data Flash58
- Data Access Overlay62
- Development Support62
- On-Chip Peripheral Units of the TC178464
- Asynchronous/Synchronous Serial Interfaces64
- High-Speed Synchronous Serial Interfaces (SSC)66
- Micro Second Channel Interface (MSC)69
  - Flexray™ Protocol Controller (E-Ray)71
  - Micro Link Interface (MLI)76
- General Purpose Timer Array (Intro)79
- Functionality of GPTA080
- Functionality of LTCA282
- Analog-To-Digital Converters83
- ADC Block Diagram83
- FADC Short Description85
- External Bus Interface88
- On-Chip Debug Support (OCDS)88
- On-Chip Debug Support88
- Real Time Trace89
- Calibration Support89
- Tool Interfaces90
- Self-Test Support90
- FAR Support90
2 CPU Subsystem91
- TC1784 Processor Subsystem91
- Central Processing Unit Features92
- CPU Diagram93
- Instruction Fetch Unit94
- Execution Unit95
- General Purpose Register File96
- CPU Implementation-Specific Features97
- Context Save Areas97
- Program Counter Register - PC97
- Interrupt System99
- Trap System99
- Memory Integrity Error Handling100
- Program Side Memories100
- Data Side Memories102
- Tricore 1.3 Compatibility105
- CPU Subsystem Registers106
- CPU Core Special Function Registers (CSFR)107
- Registers109
- CPU General Purpose Registers114
- CPU Memory Protection Registers117
- FPU Registers123
- Registers124
- Memory Integrity Registers125
- Register Descriptions127
- CPU Slave Interface (CPS) Registers142
- Register Descriptions143
- Core Debug Registers146
- Implementation Specific Reset Values148
- CPU Instruction Timing149
- Integer-Pipeline Instructions150
- Simple Arithmetic Instruction Timings150
- Multiply Instruction Timings154
- Multiply Accumulate (MAC) Instruction Timing155
- Control Flow Instruction Timing156
- Load-Store Pipeline Instructions157
- Address Arithmetic Timing157
- Control Flow Instruction Timing158
- Load Instruction Timing159
- Store Instruction Timing160
- Floating Point Pipeline Timing161
- Program Memory Interface (PMI)162
- PMI Features162
- LMB Access Priorities163
- Scratchpad RAM163
- Instruction Cache164
- Program Line Buffer165
- PMI Registers166
- PMI Register Descriptions167
- Data Memory Interface (DMI)173
- DMI Features173
- LMB Access Priorities174
- Local Data RAM (LDRAM)174
- Data Cache174
- Data Line Buffer175
- DMI Trap Generation176
- DMI Registers178
- DMI Register Descriptions179
3 System Control Unit (SCU)184
- Clock System Overview185
- Clock Generation Unit187
- Overview187
- Oscillator Circuit (OSC)188
- Phase-Locked Loop (PLL) Module190
- ERAY Phase-Locked Loop (PLL_ERAY) Module198
- Clock Control Unit206
- External Clock Output208
- CGU Registers213
- Module Clock Generation232
- Clock Control Register CLC233
- Reset Operation245
- Overview245
- Reset Types245
- Reset Sources Overview246
- Module Reset Behavior246
- General Reset Operation247
- Reset State Machine248
- Reset Counters (RSTCNTA and RSTCNTD)248
- De-Assertion of a Reset250
- Example1250
- Example2250
- Example3250
- Reset Triggers250
- Specific Reset Triggers251
- Configurable Reset Triggers251
- Debug Specific Behavior251
- EEC Reset Specific Behavior251
- Reset Controller Registers252
- Status Registers252
- Configuration Registers254
- External Interface259
- External Service Requests (Esrx)259
- Esrx as Reset Request Trigger259
- Esrx as Reset Output260
- ESR Registers261
- External Request Unit (ERU)268
- Introduction268
- External Request Select Unit (ERS)270
- ERU Pin Connections270
- Event Trigger Logic (ETL)271
- Connecting Matrix273
- Output Gating Unit (OGU)275
- ERU Output Connections277
- External Request Unit Registers279
- Power Management294
- Power Management Overview294
- Power Management Modes295
- Idle Mode295
- Sleep Mode296
- Power Management Control and Status Register, PMCSR296
- Software Boot Support299
- Configuration Done with Start-Up299
- Start-Up Configuration Options299
- Start-Up Registers300
- Start-Up Status Register300
- ECC Error Handling303
- ECC Software Testing Support303
- ECC Registers304
- Die Temperature Measurement310
- Die Temperature Sensor Register311
- Watchdog Timer313
- Watchdog Timer Overview313
- Features of the Watchdog Timer313
- The Endinit Function314
- Password Access to WDT_CON0316
- Modify Access to WDT_CON0317
- Access to Endinit-Protected Registers318
- Timer Operation318
- Timer Modes318
- WDT Reset Behavior320
- WDT Operation During Power-Saving Modes321
- Suspend Mode Support322
- Watchdog Timer Registers322
- Watchdog Timer Control Register 0322
- Watchdog Timer Control Register 1322
- Watchdog Timer Status Register326
- Emergency Stop Output Control329
- Emergency Stop Register331
- Interrupt Generation333
- Interrupt Control Registers334
- NMI Trap Generation345
- Trap Control Registers346
- Miscellaneous System Control Register355
- GPTA Input IN1 Control355
- Identification Registers357
- SCU Kernel Registers362
- SCU Address Area368
4 On-Chip System Buses and Bus Bridges369
- What Is New370
- Local Memory Bus371
- Overview371
- Transaction Types371
- Single Transfers371
- Block Transfers372
- Atomic Transfers372
- Address Alignment Rules372
- Reaction of a Busy Slave372
- LMB Basic Operation373
- Local Memory Bus Controller Unit374
- Basic Operation374
- LMB Bus Arbitration374
- LMB Bus Default Master375
- LMB Bus Error Handling375
  - LMB Bus Control Unit Registers376
    - LMB Bus Control Unit Control Registers378
- Local Memory Bus to FPI Bus Interface (LFI Bridge)384
- Functional Overview384
- LMB to FPI Bridge Control Registers386
- LFI Register Description387
- System Peripheral Bus389
- Overview389
- Bus Transaction Types391
- Reaction of a Busy Slave391
- Address Alignment Rules392
- FPI Bus Basic Operations392
- FPI Bus Control Unit (SBCU)394
- FPI Bus Arbitration394
- Arbitration on the System Peripheral Bus394
- Starvation Prevention396
- FPI Bus Error Handling396
- BCU Debug Support399
- Address Triggers399
- Signal Status Triggers400
- Grant Triggers401
- Combination of Triggers402
- BCU Breakpoint Generation Examples402
  - System Bus Control Unit Registers405
- SBCU ID Register Description407
- SBCU Control Registers Descriptions408
- SBCU Error Registers Descriptions409
- SBCU OCDS Registers Descriptions413
- SBCU Service Request Control Register Description426
- On Chip Bus Master TAG Assignments427
5 Program Memory Unit (PMU)428
- Bootrom430
- Addressing430
- Firmware Program Structure430
- Overlay RAM and Data Acquisition431
- Internal Overlay Memory431
- Online Data Acquisition (OLDA)431
- Access Performance432
- Overlay Memory Control Register432
- Emulation Memory Interface434
- PMU ID Register435
- Tuning Protection436
- Program and Data Flash437
- Introduction437
- Architectural and Operational Overview441
- Sector and441
- Data Flash and EEPROM Emulation442
- Operational Overview444
- Flash Access Control and Performance451
- Functional Description453
- Address Mapping453
- Basic Operating Modes455
- Command Sequence Definitions455
- Functional Command Description458
- Sector, Page and Block Addressing467
- Register Addresses and Access Restrictions470
- Flash Status Definition473
- Flash Configuration Control480
- Flash Identification Register486
- Error Correction and Margin Control487
- Dynamic Error Correction487
- Margin Check Control488
- Read and Write Protection491
- Read Protection491
- Write and OTP Protection494
- Protection Configuration Indication495
- User Configuration Blocks and503
- Interrupt, Error and Operation Control505
- Interrupt Control505
- Trap Control505
- Handling Errors During Operation506
- Handling Errors During Startup511
- Application Hints and Guidelines513
- Power Supply and Reset516
- Power Supply516
- Flash Power Consumption516
- Flash Sleep Mode516
- Reset Control518
6 Data Access Overlay (OVC)522
- Basic Overlay Control522
- Online Data Acquisition (OLDA) and Its Overlay525
- Enable Control of Overlay Blocks525
- Target and Overlay Memories526
- Target Memories526
- Internal Overlay Memory526
- Emulation Overlay Memory527
- External Overlay Memory527
- Change of Overlay Parameters and Overlay Start527
- Block Priority and Access Performance528
- Overlay Control Registers528
7 Bootrom Content543
- Start-Up Mode Selection543
- Internal Start544
- External Start544
- Bootstrap Loading545
- Common Procedures for All Bootloaders545
- ASC Bootstrap Loader546
- CAN Bootstrap Loader547
- Alternate Boot Modes548
- Header Check in Alternate Boot Modes548
- Startup Errors Handling551
- Notes and Usage Hints552
- Conditions Upon User Code Start552
- Rams Handling552
- Influencing the Next SSW-Execution552
8 Memory Maps553
- What Is New554
- How to Read the Address Maps555
- Contents of the Segments557
- Address Map of the FPI Bus System559
- Segments 0 to 14559
- Segment 15564
- Address Map of the Local Memory Bus (LMB)570
- Memory Module Access Restrictions575
- Side Effects from Modules to LDRAM576
9 General Purpose I/O Ports and Peripheral I/O Lines (Ports)577
- Basic Port Operation577
- Description Scheme for the Port IO Functions578
- Description of the Port Operation579
- Port Register Description581
- Port Input/Output Control Registers584
- Pad Driver Mode Register589
- Port Output Register592
- Port Output Modification Register593
- Emergency Stop Register595
- Port Input Register596
- Port 0597
- Port 0 Configuration597
- Port 0 Function Table597
- Port 0 Registers602
- Port 0 Pad Driver Mode Register and Pad Classes603
- Port 0 Emergency Stop Register603
- Port 1604
- Port 1 Configuration604
- Port 1 Function Table605
- Port 1 Registers610
- Port 1 Output Register610
- Port 1 Output Modification Register610
- Port 1 Input/Output Control Register 12611
- Port 1 Input Register611
- Port 1 Pad Driver Mode Register and Pad Classes611
- Port 1 Emergency Stop Register612
- Port 2613
- Port 2 Configuration613
- Port 2 Function Table613
- Port 2 Registers617
- Port 2 Output Register617
- Port 2 Output Modification Register617
- Port 2 Input Register617
- Port 2 Pad Driver Mode Register and Pad Classes618
- Port 2 Emergency Stop Register618
- Port 3619
- Port 3 Configuration619
- Port 3 Function Table620
- Port 3 Registers625
- Port 3 Pad Driver Mode Register and Pad Classes626
- Port 3 Emergency Stop Register627
- Port 4628
- Port 4 Configuration628
- Port 4 Function Table628
- Port 4 Registers629
- Port 4 Output Register630
- Port 4 Output Modification Register630
- Port 4 Input/Output Control Register X (X = 4, 8 and 12)630
- Port 4 Input Register630
- Port 4 Emergency Stop Register630
- Port 4 Pad Driver Mode Register and Pad Classes631
- Port 5632
- Port 5 Configuration632
- Port 5 Function Table633
- Port 5 Registers637
- Port 5 Emergency Stop Register637
- Port 5 Pad Driver Mode Register and Pad Classes638
- Port 6639
- Port 6 Registers640
- Port 6 Functions641
- Port 6 Pad Driver Mode Register642
- Port 6 Emergency Stop Register642
- Port 7643
- Port 7 Registers643
- Port 7 Functions644
- Port 7 Pad Driver Mode Register649
- Port 7 Emergency Stop Register649
- Port 8650
- Port 8 Registers650
- Port 8 Functions651
- Port 8 Pad Driver Mode Register655
- Port 8 Emergency Stop Register655
- Port 9656
- Port 9 Registers656
- Port 9 Functions657
- Port 9 Pad Driver Mode Register659
- Port 9 Emergency Stop Register659
- Port 10660
- Port 10 Registers660
- Port 10 Functions661
- Port 10 Pad Driver Mode Register665
- Port 10 Emergency Stop Register665
10 Peripheral Control Processor (PCP)666
- PCP Feature/Enhancement History List666
- Switchable Core Clock Ratio667
- Peripheral Control Processor Overview667
- High Integrity Operation667
- PCP Architecture668
- PCP Processor669
- PCP Code Memory670
- CMEM Protection670
- PCP Parameter RAM670
- PRAM Protection671
- FPI Bus Interface671
- PCP Interrupt Control Unit and Service Request Nodes671
- PCP Programming Model673
- General Purpose Register Set of the PCP673
- Register R0674
- Registers R1, R2, and R3674
- Registers R4 and R5674
- Register R6675
- Register R7676
- Contexts and Context Models678
- Context Models678
- Context Save Area681
- Context Restore Operation for CR6 and CR7684
- Context Save Operation for CR6 and CR7688
- Initialization of the Contexts691
- Context Save Optimization691
- Channel Programs692
- Channel Restart Mode692
- Channel Resume Mode693
- PCP Operation695
- PCP Initialization695
- Channel Invocation and Context Restore Operation695
- Channel Exit and Context Save Operation696
- Normal Exit696
- Error Condition Channel Exit697
- Debug Exit698
- PCP Interrupt Operation699
- Issuing Service Requests to CPU or PCP700
- PCP Interrupt Control Unit700
- PCP Service Request Nodes700
- Issuing PCP Service Requests701
- Service Request on EXIT Instruction702
- Service Request on Suspension of Interrupt702
- Service Request on Error703
- Queue Full Operation703
- PRAM Protection704
- Protection of PRAM against FPI Writes706
- Protection of PRAM against Internally Generated PRAM Writes706
- Context Save Region Protection706
- Protected Channel PRAM Protection707
- FPI Interface707
- Operation as an FPI Master707
- Operation as an FPI Slave708
- PCP Error Handling709
- PRAM Protection Violation709
- Enforced PRAM Partitioning709
- Protected Channel PRAM710
- FPI Write Window Violation710
- Channel Watchdog710
- Invalid Opcode710
- Instruction Address Error711
- Software In-System Test Support711
- Memory Integrity Error Detection712
- Instruction Set Overview713
- DMA Primitives713
- Load and Store714
- Arithmetic and Logical Instructions715
- Bit Manipulation717
- Flow Control717
- Addressing Modes718
- FPI Bus Addressing718
- PRAM Addressing719
- Bit Addressing719
- Flow Control Destination Addressing719
- FPI Interface721
- Access to the PCP Control Registers from the FPI Bus721
- PCP Control Register Protection721
- Access to the PRAM from the FPI Bus722
- Access to the CMEM from the FPI Bus722
- Debugging the PCP724
- PCP Registers726
- PCP Registers Address Space729
- Registers730
- PCP Clock Control Register, PCP_CLC730
- PCP Module Identification Register, PCP_ID731
- PCP Control and Status Register, PCP_CS732
- PCP Error/Debug Status Register, PCP_ES734
- PCP Interrupt Control Register, PCP_ICR736
- PCP Interrupt Threshold Register, PCP_ITR739
- PCP Interrupt Configuration Register, PCP_ICON740
- PCP Stall Status Register, PCP_SSR742
- SIST Mode Access Control Register, PCP_SMACON744
- Register Protection Register, PCP_RPROT745
- CMEM Protection Register, PCP_CPROT746
- PRAM Protection Register, PCP_PPROT747
- FPI Write Window Register, PCP_FWWIN751
- PCP Service Request Control Registers M, PCP_SRC[1:0]752
- PCP Service Request Control Registers M, PCP_SRC[3:2]754
- PCP Service Request Control Registers M, PCP_SRC[8:4]755
- PCP Service Request Control Registers M, PCP_SRC[11:9]756
- PCP Instruction Set Details758
- Instruction Codes and Fields758
- Conditional Codes759
- Instruction Fields760
- Counter Operation for COPY Instruction763
- Counter Operation for BCOPY Instruction764
- Divide and Multiply Instructions765
- ADD, 32-Bit Addition766
- AND, 32-Bit Logical and767
- BCOPY, DMA Operation768
- CHKB, Check Bit769
- CLR, Clear Bit769
- COMP, 32-Bit Compare770
- COPY, DMA Instruction771
- DEBUG, Debug Instruction772
- DINIT, Divide Initialization773
- DSTEP, Divide Instruction774
- EXIT, Exit Instruction775
- INB, Insert Bit776
- JC, Jump Conditionally777
- JL, Jump Long Unconditional778
- LD, Load778
- LDL, Load 16-Bit Value780
- MINIT, Multiply Initialization780
- MOV, Move Register to Register781
- Multiply Instructions782
- NEG, Negate783
- NOP, no Operation783
- NOT, Logical NOT783
- OR, Logical or784
- PRAM Bit Operations785
- PRI, Prioritize786
- RL, Rotate Left787
- RR, Rotate Right787
- SET, Set Bit788
- SHL, Shift Left788
- SHR, Shift Right789
- ST, Store790
- SUB, 32-Bit Subtract791
- XCH, Exchange792
- XOR, 32-Bit Logical Exclusive or793
- Flag Updates of Instructions794
- Instruction Timing795
- Instruction Encoding799
- Programming of the PCP805
- Initial PC of a Channel Program805
- Channel Entry Table805
- Channel Resume806
- Channel Management for Small and Minimum Contexts807
- Unused Registers as Global's or Constants807
- Dispatch of Low Priority Tasks808
- Code Reuse Across Channels (Call and Return)808
- Case-Like Code Switches (Computed Go-To)809
- Simple DMA Operation809
- COPY Instruction809
- BCOPY Instruction (Burst Copy)810
- PCP Programming Notes and Tips811
- Notes on PCP Configuration811
- General Purpose Register Use811
- Use of Channel Interruption813
- Dynamic Interrupt Masking813
- Control of Channel Priority (CPPN)813
- Implementing Divide Algorithms814
- Implementing Multiply Algorithms815
- Implementation of the PCP in the TC1784817
- PCP Memories817
- BCOPY Instruction817
- PCP Reset Operation818
11 Direct Memory Access Controller (DMA)819
- What Is New819
- DMA Controller Kernel Description821
- Features822
- Definition of Terms823
- DMA Principles824
- DMA Channel Functionality825
- Shadowed Source or Destination Address825
- DMA Channel Request Control829
- DMA Channel Operation Modes830
- Error Conditions834
- Channel Reset Operation835
- Transfer Count and Move Count836
- Circular Buffer838
- Transaction Control Engine839
- Bus Switch, Bus Switch Priorities840
- DMA Module Priorities on on Chip Busses (FPI Bus, LMB Bus)842
- DMA Module: on Chip Bus Access Rights, RMW Support843
- DMA Module on Chip Bus Master Interfaces843
- DMA Module Bridge Functionality845
- On-Chip Debug Capabilities846
- Hard-Suspend Mode846
- Soft-Suspend Mode846
- Break Signal Generation847
- Interrupts849
- Channel Interrupts849
- Transaction Lost Interrupt851
- Move Engine Interrupts852
- Wrap Buffer Interrupts854
- Interrupt Request Compressor855
- Pattern Detection856
- Pattern Compare Logic858
- Pattern Detection for 8-Bit Data Width859
- Pattern Detection for 16-Bit Data Width860
- Pattern Detection for 32-Bit Data Width862
- Access Protection863
- DMA Module Registers866
- System Registers872
- General Control/Status Registers878
- Move Engine Registers897
- Channel Control/Status Registers904
- Channel Address Registers916
- DMA Module Implementation919
- DMA Request Wiring Matrix920
- Access Protection Assignment930
- Implementation-Specific DMA Registers938
- Clock Control Register940
- DMA Interrupt Registers941
- MLI Interrupt Registers942
- Address Map943
- Memory Checker Module944
- Functional Description944
- Memory Checker Module Registers946
- Memory Checker Module Control Registers947
12 LMB External Bus Unit951
- Feature List951
- Block Diagram951
- EBU Interface Signals953
- Address/Data Bus, AD[15:0]953
- Address Bus, A[20:16]953
- Chip Selects, CS[3:0]953
- Read/Write Control Lines, RD, RD/WR954
- Address Valid, ADV954
- Byte Controls, BC[1:0]954
- Wait Input, WAIT955
- EBU Reset955
- Allocation of Unused Signals as GPIO955
- Control of Pad Pull up and Pull down956
- External Bus Arbitration957
- Arbitration Modes958
- No Bus Arbitration Mode958
- Sole Master Arbitration Mode958
- Start-Up/Boot Process959
- Clocking Strategy and Local Clock Generation959
- Local Clock Divider959
- Standby Mode959
- External Busoperation960
- External Memory Regions961
- Chip Select Control964
- Programmable Device Types964
- Support for Multiplexed Device Configurations964
- Address Comparison967
- Access Parameter Selection971
- Programming Sequence Locking972
- LMB Bus Width Translation972
- Address Alignment During Bus Accesses973
- LMB Data Buffering974
- Standard Access Phases974
- Address Phase (AP)974
- Address Hold Phase (AH)975
- Command Delay Phase (CD)976
- Command Phase (CP)976
- Data Hold Phase (DH)977
- Recovery Phase (RP)977
- Asynchronous Read/Write Accesses980
- Signal List980
- Standard Asynchronous Access Phases981
- Programmable Parameters981
- Control of ADV & Other Signal Delays During Asynchronous Accesses982
- Accesses to Multiplexed Devices985
- Interfacing to Nand Flash Devices986
- NAND Flash986
- Dynamic Command Delay and Wait State Insertion991
- External Extension of the Command Phase by WAIT991
- EBU Registers995
- Clock Control Register, CLC998
- Configuration Register, MODCON999
- External Boot Configuration Control Register, EXTBOOT1001
- Address Select Register, Addrselx1002
- Bus Configuration Register, Busrconx1004
- Bus Write Configuration Register, Buswconx1007
- Bus Read Access Parameter Register, Busrapx1009
- Bus Write Access Parameter Register, Buswapx1012
- Test/Control Configuration Register, USERCON1015
13 Interrupt System1016
- Overview1016
- Service Request Nodes1018
- Service Request Control Registers1018
- General Service Request Control Register Format1018
- Request Set and Clear Bits (SETR, CLRR)1020
- Enable Bit (SRE)1020
- Service Request Flag (SRR)1020
- Type-Of-Service Control (TOS)1021
- Service Request Priority Number (SRPN)1021
- Interrupt Control Units1023
- Interrupt Control Unit (ICU)1023
- ICU Interrupt Control Register (ICR)1023
- Operation of the Interrupt Control Unit (ICU)1025
- PCP Interrupt Control Unit (PICU)1026
- Arbitration Process1027
- Controlling the Number of Arbitration Cycles1027
- Controlling the Duration of Arbitration Cycles1028
- Entering an Interrupt Service Routine1028
- Exiting an Interrupt Service Routine1029
- Interrupt Vector Table1030
- Usage of the TC1784 Interrupt System1033
- Spanning Interrupt Service Routines Across Vector Entries1033
- Configuring Ordinary Interrupt Service Routines1034
- Interrupt Priority Groups1034
- Splitting Interrupt Service Across Different Priority Levels1035
- Using Different Priorities for the same Interrupt Source1036
- Interrupt Priority 11037
- Software-Initiated Interrupts1037
- External Interrupts1037
- Service Request Node Table1038
14 System Timer (STM)1041
- Overview1041
- Operation1041
  - System Timer (STM)1041
- Resolution and Ranges1044
- Compare Register Operation1045
- Compare Match Interrupt Control1046
- STM Registers1047
- Clock Control Register1049
- Timer/Capture Registers1051
- Compare Registers1054
- Interrupt Registers1057
- STM Module Implementation1061
- On-Chip Service Request Connections1061
- STM Address Map1061
15 On-Chip Debug Support (OCDS)1063
- Overview1063
- OCDS Level 11067
- Tricore CPU OCDS Level 11068
- Basic Concept1068
- Debug Event Generation1069
- Debug Actions1070
- Tricore OCDS Registers1070
- SBCU OCDS Level 11071
  - PCP OCDS Level 11071
- Debug Interface (Cerberus)1072
- RW Mode1072
- Communication Mode1073
- Triggered Transfers1073
- Multi Core Break Switch1073
- JTAG Interface1075
- Device Access Port (DAP)1075
- DAP Telegram Format1075
- DAP Telegram Catalog1075
- Cerberus and JTAG Registers1076
16 Asynchronous/Synchronous Serial Interface (ASC)1079
- ASC Kernel Description1079
- Overview1080
- General Operation1081
- Asynchronous Operation1082
- Asynchronous Data Frames1083
- Asynchronous Transmission1085
- Asynchronous Reception1085
- RXD/TXD Data Path Selection in Asynchronous Modes1086
- Synchronous Operation1087
- Synchronous Transmission1088
- Synchronous Reception1088
- Synchronous Timing1089
- Baud Rate Generation1090
- Baud Rates in Asynchronous Mode1091
- Baud Rates in Synchronous Mode1094
- Hardware Error Detection Capabilities1095
- Interrupts1095
- ASC Kernel Registers1097
- Control Registers1098
- Data Registers1106
- ASC0/ASC1 Module Implementation1108
- Interfaces of the ASC Modules1108
- ASC0/ASC1 Module Related External Registers1110
- Clock Control Register1111
- Peripheral Input Select Register1113
- Port Control Registers1115
- Interrupt Control Registers1117
- DMA Requests1118
- Address Map1119
17 Synchronous Serial Interface (SSC)1122
- SSC Kernel Description1122
- Overview1123
- General Operation1124
- Operating Mode Selection1126
- Full-Duplex Operation1127
- SSC Kernel Registers1148
- SSC0/SSC1/SSC2 Module Implementation1164
- Micro Second Channel (MSC)1183
18 Micro Second Channel (MSC)1185
- MSC Kernel Description1185
  - Overview1185
  - Downstream Channel1187
  - Upstream Channel1203
  - I/O Control1209
    - Downstream Channel Output Control1209
    - Upstream Channel1212
  - MSC Interrupts1213
    - Data Frame Interrupt1214
- Command Frame Interrupt1214
- Time Frame Finished Interrupt1215
- Receive Data Interrupt1216
- Interrupt Request Compressor1217
- MSC Kernel Registers1218
- Module Identification Register1220
- Status and Control Registers1221
- Data Registers1241
- MSC Module Implementation1244
- Interface Connections of the MSC Module1244
- MSC0 Module-Related External Registers1246
- Clock Control1247
- Clock Control Register1249
- Fractional Divider Register1250
- Port Control1251
- Input/Output Function Selection1251
- On-Chip Connections1253
- EMGSTOPMSC Signal (from SCU)1253
- DMA Controller Service Requests1253
- Interrupt Control Registers1254
- MSC0 Address Map1255
19 Controller Area Network Controller (Multican)1257
- CAN Basics1258
- Addressing and Bus Arbitration1258
- CAN Frame Formats1259
- Data Frames1259
- Remote Frames1261
- Error Frames1263
- The Nominal Bit Time1264
  - Error Detection and Error Handling1265
- Overview1267
- Multican Module1268
- Multican Kernel Functional Description1270
- Module Structure1270
- Clock Control1273
- Port Input Control1274
- Suspend Mode1274
- CAN Node Control1276
- Bit Timing Unit1277
- Bitstream Processor1278
- Error Handling Unit1279
- CAN Frame Counter1280
- CAN Node Interrupts1280
- Message Object List Structure1282
- Basics1282
- List of Unallocated Elements1283
- Connection to the CAN Nodes1283
- List Command Panel1284
- CAN Node Analysis Features1287
- Analyze Mode1287
- Loop-Back Mode1287
- Bit Timing Analysis1288
- Message Acceptance Filtering1290
- Receive Acceptance Filtering1290
- Transmit Acceptance Filtering1291
- Message Postprocessing1293
- Message Object Interrupts1293
- Pending Messages1295
- Message Object Data Handling1297
- Frame Reception1297
- Frame Transmission1300
- Message Object Functionality1303
- Standard Message Object1303
- Single Data Transfer Mode1303
- Single Transmit Trial1303
- Message Object FIFO Structure1304
- Receive FIFO1306
- Transmit FIFO1307
- Gateway Mode1308
- Foreign Remote Requests1310
- Multican Kernel Registers1311
- Global Module Registers1314
- CAN Node Registers1326
- Message Object Registers1344
- Multican Module Implementation1365
- Interfaces of the Multican Module1365
- Multican Module External Registers1366
- Module Clock Generation1367
- CAN Clock Control Register1368
- Port and I/O Line Control1370
- Input/Output Function Selection in Ports1370
- Node Receive Input Selection1370
- DMA Request Outputs1371
- Interrupt Control1372
- CAN Service Request Control Register1374
- Multican Module Register Address Map1375
20 Flexray™ Protocol Controller (E-Ray)1377
- E-Ray Kernel Description1377
- Overview1378
- Definitions1379
- Block Diagram1379
- Programmer's Model1382
- Register Map1382
- E-Ray Kernel Registers1384
- Customer Registers1392
- Special Registers1399
- Service Request Registers1413
- Communication Controller Control Registers1460
- Communication Controller Status Registers1487
- Message Buffer Control Registers1510
- Message Buffer Status Registers1517
- Identification Registers1538
- Input Buffer1540
- Output Buffer1551
- Functional Description1568
- Communication Cycle1568
- Static Segment1568
- Dynamic Segment1569
- Symbol Window1569
- Network Idle Time (NIT)1569
  - Configuration of Network Idle Time (NIT) Start and Offset Correction Start1569
- Communication Modes1571
- Clock Synchronization1571
- Global Time1571
- Local Time1571
- Synchronization Process1572
- External Clock Synchronization1573
- Error Handling1574
- Clock Correction Failed Counter1574
- Passive to Active Counter1575
- HALT Command1575
- FREEZE Command1575
- Communication Controller States1577
- Communication Controller State Diagram1577
- DEFAULT_CONFIG State1580
  - Monitor_Mode1580
  - READY State1581
  - WAKEUP State1581
  - STARTUP State1586
  - Startup Time-Outs1589
  - Path of Leading Coldstart Node (Initiating Coldstart)1590
  - NORMAL_PASSIVE State1592
  - NORMAL_ACTIVE State1592
  - HALT State1593
  - Network Management1594
  - Filtering and Masking1594
- FIFO Function1602
  - Description1602
  - Configuration of the FIFO1603
  - Access to the FIFO1604
- Message Handling1604
  - Host Access to Message RAM1604
  - Minimum F CLC_ERAY1615
  - Flexray™ Protocol Controller Access to Message RAM1619
- Message RAM1621
  - Header Partition1622
  - Data Partition1625
  - ECC Check1626
- Host Handling of Errors1629
  - Self-Healing1629
  - CLEAR_RAMS Command1629
  - Temporary Unlocking of Header Section1629
  - Module Service Request1631
  - Restrictions1634
- Message Buffers with the same Frame ID1634
- E-Ray Module Implementation1635
- Interconnections of the E-Ray Module1635
- Input/Output Function Selection1636
  - Port Control and Connections1636
- E-Ray Connections with DMA1638
- On-Chip Connections1638
- E-Ray Connections with the External Request Unit of SCU1639
- E-Ray Connections with the ECC Error Handling Unit of SCU1639
- E-Ray Connections with the External Clock Output of SCU1639
- Clock Control Register1640
- Interrupt Registers1641
21 General Purpose Timer Array (GPTA ® V5)1654
- GPTA ® V5 Overview1656
- Functionality of GPTA01657
- Functionality of LTCA21659
- GPTA0 Kernel Description1660
- GTPA Units1661
- Clock Generation Cells1662
- Filter and Prescaler Cell (FPC)1664
- Phase Discrimination Logic (PDL)1673
- Duty Cycle Measurement Cell (DCM)1678
- Digital Phase Locked Loop Cell (PLL)1682
- Clock Distribution Cell (CDC)1687
- Signal Generation Cells1690
- Global Timers (GT)1690
- Global Timer Cell (GTC)1707
- Local Timer Cell (LTC00 to LTC62)1719
- Local Timer Cell LTC631731
- Coherent Update1737
- Input/Output Line Sharing Block (IOLS)1750
- FPC Input Line Selection1754
- GTC and LTC Output Multiplexer Selection1755
- On-Chip Trigger and Gating Output Multiplexer Selection1760
- GTC Input Multiplexer Selection1763
- LTC Input Multiplexer Selection1768
- Multiplexer Register Array Programming1773
- Interrupt Sharing Block (IS)1775
- FPC Algorithm1778
- PDL-Algorithm1783
- DCM-Algorithm1787
- PLL-Algorithm1790
- GT-Algorithm1792
- GTC-Algorithm1793
  - LTC-Algorithm for Cells 0 to 621798
  - LTC Algorithm for Cell 631806
- GPTA0 Kernel Registers1812
  - Gpta1818
  - GPTA ® V5 Identification Register1818
- FPC Registers1819
- Phase Discriminator Registers1823
- Duty Cycle Measurement Registers1825
- Digital Phase Locked Loop Registers1828
- Global Timer Registers1832
- Clock Bus Register1834
- Global Timer Cell Registers1836
- LTCA Kernel Description1881
- Local Timer Cell (LTC00 to LTC63)1882
- Output Multiplexer1884
- LTC Input Multiplexing Scheme1889
- Multiplexer Register Array Programming1892
- Interrupt Sharing Block (IS)1895
- LTCA Kernel Registers1897
  - Bit Protection1898
  - I/O Sharing Block Registers1910
- LTC Input Multiplexer Control Registers1917
- GPTA ® V5 Module Implementation1921
- Interconnections of GPTA0/LTCA2 Units1921
- I/O Port Line Assignment1923
- Port Control and Connections1923
- Input/Output Function Selection1925
  - Emergency Control of GPTA1927
- Clock Bus Connections1929
- MSC Controller Connections1929
- On-Chip Connections1929
- Connections to SCU, Multican, FADC, DMA, Ports1935
- Clock Control Registers1940
- Fractional Divider Register1941
- Limits of Cascading Gtcs and Ltcs1945
- Interrupt Registers1946
- GPTA Register Address Map1947
22 Micro Link Interface (MLI)1950
- Functional Description1951
- General Introduction1951
- MLI Overview1951
- Naming Conventions1953
- MLI Communication Principles1955
- MLI Frame Structure1959
- General Frame Layout1960
- Copy Base Address Frame1961
- Write Offset and Data Frame1962
- Optimized Write Frame1963
- Discrete Read Frame1964
- Optimized Read Frame1965
- Command Frame1966
- Answer Frame1967
- Handshake Description1968
- Handshake Signals1970
- Error-Free Handshake1970
- Ready Delay Time1971
- Non-Acknowledge Error1972
- Signal Timing1973
- Parity Generation1975
- Address Prediction1975
- Module Kernel Description1976
- Frame Handling1976
- Copy Base Address Frame1977
- Write/Data Frames1979
- Read Frames1983
- Answer Frame1988
- Command Frame1990
- General MLI Features1993
- Parity Check and Parity Error Indication1993
- Non-Acknowledge Error1996
- Address Prediction1996
- Automatic Data Mode1997
- Memory Access Protection1998
- Triggered Command Transfers1998
- Transmit Priority2000
- Transmission Delay2000
- Interface Description2001
- Transmitter I/O Line Control2003
- Receiver I/O Line Control2003
- Connecting Several MLI Modules2005
- MLI Service Request Generation2007
- Transmitter Events2009
- Parity/Time-Out Error Event2010
- Normal Frame Sent X Event2010
- Command Frame Sent Events2011
- Receiver Events2012
- Discarded Read Answer Event2012
- Memory Access Protection/Parity Error Event2013
- Normal Frame Received/Move Engine Terminated Event2014
- Interrupt Command Frame Event2015
- Command Frame Received Event2016
- Baud Rate Generation2017
- Automatic Register Overwrite2018
- Operating the MLI2019
- Connection Setup2020
- Local Transmitter and Pipe Setup2021
- Remote Receiver Setup2021
- Remote Transmitter and Local Receiver Setup2022
- Delay Adjustment2023
- Connection to DMA Mechanism2025
- Connection of MLI to SPI2025
- MLI Kernel Registers2027
- General Module Registers2030
- General Status/Control Registers2034
- Access Protection Registers2041
- Transmitter Control/Status Registers2044
- Transmitter Pipe X Address Offset Register2055
- Transmitter Interrupt Registers2059
- Receiver Control/Status Registers2065
- Receiver Address/Data Registers2069
- Receiver Interrupt Registers2072
- Implementation of the MLI0 in TC17842079
  - MLI Module External Registers2081
- Break Signals2087
- Access Protection2087
  - MLI Module External Registers2091
- Break Signals2098
- Access Protection2098
- MLI0/MLI1 Transfer Window Address Maps2099
- MLI0 Address Map2100
23 Analog to Digital Converter (ADC)2107
- Introduction2107
- ADC Block Diagram2108
- Feature Set2109
- Abbreviations2110
- ADC Kernel Overview2111
- Conversion Request Unit2113
- Conversion Result Unit2115
- Interrupt Structure2116
- Electrical Models2117
- Input Signal Path2117
- Reference Path2118
- Transfer Characteristics and Error Definitions2120
- Operating the ADC2121
- Register Overview2122
- Mode Control2127
- Module Activation and Power Saving Modes2129
  - Clocking Scheme2130
  - ADC Module Registers2131
    - Kernel State Configuration Register2132
  - General ADC Kernel Registers2135
  - Request Source Arbiter2148
    - Request Source Priority2149
    - Conversion Start Modes2150
  - Arbiter Registers2153
    - Arbitration Slot Enable Register2153
    - Request Source Priority Register2154
  - Scan Request Source Handling2156
- Scan Request Source Registers2160
  - Conversion Request Control Registers2160
  - Conversion Request Pending Registers2162
  - Conversion Request Mode Registers2163
- Sequential Request Source Handling2166
  - Overview2167
  - Sequential Source Operation2168
  - Request Source Event and Interrupt2169
- Sequential Source Registers2171
  - Queue Mode Registers2171
  - Queue Status Registers2174
  - Queue 0 Registers2176
  - Queue Backup Registers2178
  - Queue Input Registers2180
- Channel-Related Functions2182
  - Input Classes2182
  - Reference Selection2183
  - Alias Feature2183
  - Limit Checking2184
  - Channel Event Interrupts2186
- Channel-Related Registers2187
- Channel Control Registers2187
- Input Class Registers2189
- Alias Register2190
- Limit Check Boundary Registers2191
- Channel Flag Register2192
- Channel Flag Clear Register2193
- Channel Event Node Pointer Registers2194
- Conversion Result Handling2196
- Storage of Conversion Results2196
- Wait-For-Read Mode2198
- Result Event Interrupts2199
- Result FIFO Buffer2200
- Data Reduction Filter2202
- Conversion Result-Related Registers2204
- Result Registers 1 to 152206
- Valid Flag Register2208
- Result Control Registers2209
- Event Flag Register2211
- Event Flag Clear Register2213
- Event Node Pointer Registers2214
- Multiplexer Test Support2217
- Synchronized Conversions for Parallel Sampling2221
- Equidistant Sampling2224
- Access Protection2226
- Broken Wire Detection2227
- Additional Feature Registers2229
- Access Protection Register2229
- Synchronization Control Register2234
- Broken Wire Detection Enable Register2236
- Broken Wire Detection Configuration Register2237
- Implementation2238
- Request Sources in TC17842238
- Address Map2238
- ADC Module Connections2239
- ADC0 Connections2240
- ADC1 Connections2246
- Service Request Connections2252
- Kernel Synchronization2253
24 Fast Analog to Digital Converter (FADC)2254
- FADC Short Description2255
- FADC Kernel Description2258
- Analog Input Stage Configurations2258
- Result Representation2260
- Conversion Timing2260
- Channel Triggers2261
- Channel Timer2262
- Conversion Control2265
- Static Channel Priority2265
- Dynamic Priority Assignment2265
- Clock Generation2266
- Suspend Mode Behavior2266
- Alias Feature2267
- Data Reduction Unit2268
- Filter Block Structure2269
- Filter Block Operation2269
- Filter Concatenation2270
- Width of Result Registers2272
- Neighbor Channel Trigger2273
- Calibration2274
- Offset Calibration2275
- Interrupt Generation2276
- FADC Register Description2279
- System Registers2283
- Fractional Divider Register2284
- Module Identification Register2286
- Global Registers2288
- Conversion Request Status Register2288
- Flag Modification Register2290
- Neighbor Channel Trigger Register2292
- Global Control Register2295
- Alias Register2299
- Channel Registers2301
- Channel Configuration Registers2301
- Analog Control Registers2305
- Conversion Result Registers2307
- Filter Registers2308
- Filter Control Registers2308
- Current Result Registers2311
- Intermediate Result Registers2313
- Final Result Registers2315
- Implementation of FADC2317
  - Register Overview2317
  - Interfaces of the FADC Module2318
  - FADC Connections2319
  - Service Request Connections2320
    - Clock Control2322
    - User´s Manual L-27 V1.12349

Architecture	TriCore
Core	TriCore
Flash Memory	4 MB
RAM	2 MB
Number of Cores	1
Operating Voltage	3.3 V
Package Type	LQFP
Ethernet	Yes
Temperature Range	-40°C ~ 125°C
ADC Resolution	10 bit

Infineon Technologies TC1784 - User Manual

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Infineon Technologies TC1784 Specifications

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