Infineon Technologies TC1784 - Port Input Register

TC1784
General Purpose I/O Ports and Peripheral I/O Lines (Ports)
User´s Manual 9-20 V1.1, 2011-05
Ports, V1.1
Note: Only Ports 0, 3, and 5 are 16-bit wide ports. The Pn_ESR registers of the other
ports have a reduced number of bits (see Pn_ESR register descriptions in the
corresponding port sections).
9.2.6 Port Input Register
The logic level of a GPIO pin can be read via the read-only port input register Pn_IN.
Reading the Pn_IN register allways returns the current logical value at the GPIO pin
independently whether the pin is selected as input or output.
Note: The Pn_IN registers of the ports with less then 16 pins, have less than 16 Px bits
(see Pn_IN register descriptions in the corresponding port sections).
0 [31:16] r Reserved
Read as 0; should be written with 0.
Pn_IN (n=0-10)
Port n Input Register (F000 0C24
H
+n*100
H
) Reset Value: 0000 XXXX
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh
Field Bits Type Description
Px
(x = 0-15)
xrhPort n Input Bit x
This bit indicates the level at the input pin Pn.x.
0
B
The input level of Pn.x is 0.
1
B
The input level of Pn.x is 1.
0 [31:16] r Reserved
Read as 0.
Field Bits Type Description