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Details the key features of the XBurst®2 CPU for the X2000 platform, including ISA and pipeline architecture.
Summarizes the CP0 registers, grouped by function and number, for the XBurst2 core.
Describes the format of CP0 registers, including field types and R/W access properties.
Provides detailed descriptions of various CP0 registers, including configuration and status registers.
Details the priority order for exceptions occurring simultaneously in the XBurst CPU.
Specifies the memory locations for exception handler entries based on exception type.
Outlines the steps involved in entering and returning from exception handler routines.
Introduces the on-chip Memory Management Unit (MMU) and its role in address translation.
Describes the 32-bit virtual address space and its segmentation across different operating modes.
Explains the Translation Lookaside Buffer (TLB) structure and its function in memory management.
Details the features of the L1 instruction and data caches, including size and associativity.
Describes the unified L2 cache for symmetric cores, including size and associativity.
Explains the hardware initialization of CP0 state, TLB, and caches upon reset.
Details the software initialization requirements for general purpose registers after reset.
Introduces the CCU, its functions for SMP systems, and register accessibility.
Lists and describes the registers within the Core Control Unit (CCU).
Provides examples for safe manipulation and configuration of CCU registers.
Provides an overview of EJTAG debug logic, features, and modes.
Explains how to detect if the processor is operating in debug mode using the DM bit.
Describes the five methods to enter the processor's debug mode.
Details the three ways to exit debug mode and return to normal operation.
Explains hardware breakpoints for instruction and data access comparison.
Defines the conditions required for a breakpoint match on instructions or data accesses.
Describes how to set up breakpoints to generate debug exceptions upon matching conditions.
Explains the functionality and states of the Test Access Port controller.
Details the various registers used for EJTAG debug control and status.
Covers debug exception priorities, vector locations, and general processing flow.
Explains how exceptions are handled when the processor is in debug mode.
Describes the behavior and organization of the Accelerated EJTAG Mode (ACC Mode).
General| Architecture | MIPS32 |
|---|---|
| Cores | 1 |
| Threads | 1 |
| Clock Speed | 1.2 GHz |
| Manufacturing Process | 40 nm |
| Instruction Set | MIPS32 |
| L2 Cache | 128 KB |
| FPU | Yes |
| L1 Cache | 32 KB |
| SIMD | Not supported |
| Power Consumption | Low Power |
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