Name: Ingenic X1000
Brand: Ingenic
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X1000

IoT Application Processor

Programming Manual

Release Date: Jan. 13, 2016

Table of Contents3
Tables21
Section 1 Overview29
Overview30
Block Diagram30
Features30
CPU Core30
Figure 1-1 X1000 Diagram30
Image Core31
Display/Camera/Audio31
Memory Interface33
System Functions34
Peripherals35
Bootrom37
Section 2 Core Functions38
Cpu39
Block Diagram39
Figure 2-1 Structure of CPU Core40
Extra Features of the CPU Core41
Instruction Cycles41
Pmon44
Fundamental45
Partial Kernel Mode45
Section 3 Image Core46
Jpeg47
Overview47
Register Definition47
Task Trigger (TRIG)47
VDMA Status (STAT)48
Global Control Information48
JPGC Trigger49
JPGC Status50
Bitstream Buffer Address50
Component 0 Plane Buffer Address51
Component 1 Plane Buffer Address51
Component 2 Plane Buffer Address52
Component 3 Plane Buffer Address52
MCU Number53
Re-Sync-Marker Gap Number53
Component Configure Information53
EFE Control54
Encoder Slice Geometry Information54
RAW Plane Source Buffer Address55
RAW Destination Buffer Basement Address55
RAW Plane Stride56
Huffman Base Table56
Huffman MIN Table56
Quantization Table 056
Huffman Symbol Table57
Huffman ENC Table57
Section 4 Display/Camera/Audio58
SLCD Controller59
Overview59
Pin Description59
Table 4-1 SLCD Pins Description59
Block Diagram60
Register Description60
Figure 4-1 Block Diagram of SLCD60
Table 4-2 Registers Memory Map-Address Base61
Table 4-3 SLCD Controller Registers Description61
Configure Register (LCDCFG)63
Control Register (LCDCTRL)63
Status Register (LCDSTATE)64
OSD Control Register (LCDOSDCTRL)65
Background0 Color Register (LCDBGC0)65
Display Area Horizontal Start/End Point (LCDDAH)66
Display Area Vertical Start/End Point (LCDDAV)66
Foreground 0 XY Position Register (LCDXYP0)66
Foreground 0 Size Register (LCDSIZE0)67
REV Signal Setting (LCDREV)67
Interrupt ID Register (LCDIID)67
Descriptor Address Registers (Lcddax)68
Source Address Registers (LCDSA)69
Frame ID Registers (Lcdfidx)70
DMA Command Registers (Lcdcmdx)70
DMA OFFSIZE Registers (Lcdoffsx)71
DMA Page Width Registers (Lcdpwx)71
DMA Commend Counter Registers (Lcdcnumx)72
DMA Commend Counter Registers (Lcdcposx)72
Foreground X Size in Descriptor (Lcddessizex)73
Priority Level Threshold Configure Register (LCDPCFG)73
LCD Arbiter Priority(LCD_PCFG_ARB)74
SLCD Configure Register (MCFG)75
SLCD Configure New Register (MCFG_NEW)76
SLCD Control Register (MCTRL)79
SLCD Status Register (MSTATE)80
SLCD Data Register (MDATA)80
SLCD Wait Time Register (WTIME)81
Address Setup and Hold Time Register (TASH)81
Slow Mode Wait Time Register(SMWT)81
SLCD Controller Operation82
Set SLCD Controller AHB Clock and Pixel Clock82
Enabling the Controller82
Disabling the Controller82
Resetting the Controller83
Frame Buffer83
System Memory Format83
Data Format83
Command Format85
Transfer Mode86
DMA Transfer Mode86
Register Transfer Mode87
Timing87
Parallel Timing87
Serial Timing88
Operation Guide88
DMA Operation88
Register Operation89
Camera Interface Module90
Overview90
Features90
Pin Description90
CIM Special Register90
Table 5-1 Camera Interface Pins Description90
Table 5-2 CIM Registers90
CIM Configuration Register (CIMCFG)91
CIM Control Register (CIMCR)94
CIM Control Register 2 (CIMCR2)95
CIM Status Register (CIMST)96
CIM Interrupt Mask Register (CIMIMR)97
CIM Interrupt ID Register (CIMIID)98
CIM Descriptor Address (CIMDA)99
CIM Frame Buffer Address Register (CIMFA)99
CIM Frame ID Register (CIMFID)99
CIM DMA Command Register (CIMCMD)100
CIM Window Size (CIMWSIZE)101
CIM Window Offset (CIMWOFFSET)101
CIM Frame Size Register (CIMFS)101
CIM Data Sample Modes102
Gated Clock Mode102
Table 5-3 the Modes and the Corresponding Signals Used102
ITU656 Interlace Mode103
ITU656 Progressive Mode104
DMA Descriptors104
Figure 5-1 ITU656 Progressive Mode104
Software Operation105
Enable CIM with DMA105
Operations for RXFIFO Overflow105
Operations for Frame Size Error105
Audio Interface Controller107
Overview107
Block Diagram108
Features108
Figure 6-1 AIC Block Diagram108
Interface Diagram109
Figure 6-2 Interface to an External Master Mode I2S/MSB-Justified CODEC Diagram109
Figure 6-3 Interface to an External Slave Mode I2S/MSB-Justified CODEC Diagram109
Signal Descriptions110
Table 6-1 AIC Pins Description110
Figure 6-4 Interface to a HDMI Transmitter Via SPDIF Diagram110
Register Descriptions111
Table 6-2 AIC Registers Description111
AIC Configuration Register (AICFR)112
AIC Common Control Register (AICCR)114
AIC I2S/MSB-Justified Control Register (I2SCR)117
AIC Controller FIFO Status Register (AICSR)118
AIC I2S/MSB-Justified Status Register (I2SSR)120
AIC I2S/MSB-Justified Clock Divider Register (I2SDIV)121
AIC FIFO Data Port Register (AICDR)121
SPDIF Enable Register (SPENA)122
SPDIF Control Register (SPCTRL)122
SPDIF State Register (SPSTATE)123
SPDIF Configure 1 Register (SPCFG1)124
SPDIF Configure 2 Register (SPCFG2)125
SPDIF FIFO Register (SPFIFO)126
Serial Interface Protocol127
I2S and MSB-Justified Serial Audio Format127
Figure 6-5 I2S Data Format (A: LR Mode)127
Figure 6-6 I2S Data Format (B: RL Mode)128
Figure 6-7 MSB-Justified Data Format (C: LR Mode)128
Figure 6-8 MSB-Justified Data Format (D: RL Mode)128
Audio Sample Data Placement in SDATA_IN/SDATA_OUT129
Table 6-3 Sample Data Bit Relate to SDATA_IN/SDATA_OUT Bit129
SPDIF Protocol130
Figure 6-9 Block Format130
Figure 6-10 Sub-Frame Format in PCM Mode130
I2S Operation131
Initialization131
Figure 6-11 Sub-Frame Format in Non-PCM Mode131
External CODEC Registers Access Operation132
Audio Replay132
Audio Record133
Fifos Operation134
Figure 6-12 Transmitting/Receiving FIFO Access Via APB Bus134
Data Flow Control135
Audio Samples Format136
Figure 6-13 One Channel (Left) and Two Channels (Right) Mode (16 Bits Packed Mode)136
Figure 6-14 Four Channels (Left) and Six Channels (Right) Mode (16 Bits Packed Mode)137
Figure 6-15 Eight Channels Mode (16 Bits Packed Mode)137
Figure 6-16 One Channel (Left) and Two Channels (Right) Mode137
Serial Audio Clocks and Sampling Frequencies138
Figure 6-17 Four Channels (Left) and Six Channels (Right) Mode138
Figure 6-18 Eight Channels Mode138
Table 6-4 Audio Sampling Rate, BIT_CLK and SYS_CLK Frequencies139
Table 6-5 BIT_CLK Divider Setting140
Figure 6-19 SYS_CLK, BIT_CLK and SYNC Generation Scheme140
Table 6-6 Approximate Common Multiple of SYS_CLK for All Sample Rates141
Table 6-7 CPM/AIC Clock Divider Setting for Various Sampling Rate if PLL = 270.64Mhz141
Interrupts142
Table 6-8 PLL Parameters and Audio Sample Errors for Exclk=12Mhz142
SPDIF Guide143
Set SPDIF Clock Frequency143
PCM Audio Mode Operation (Reference IEC60958)143
Non-PCM Mode Operation (Reference IEC61937)143
Disable Operation144
PCM Interface145
Overview145
Pin Description145
Table 7-1 PCM Interface Pins Description145
Block Diagram146
Registers146
Registers Memory Map147
Register Description147
Table 7-3 PCM Registers Description147
PCM Interface Timing153
Short Frame SYN153
Figure 7-1 Short Frame SYN Timing (Shown with 16Bit Sample)153
Figure 7-2 Short Frame SYN Timing (Shown with 16Bit Sample)153
Long Frame SYN154
Multi-Slot Operation154
Figure 7-3 Long Frame SYN Timing (Shown with 16Bit Sample)154
Figure 7-4 Long Frame SYN Timing (Shown with 16Bit Sample)154
Figure 7-5 Multi-Slot Frame SYN Timing (Shown with Two Slots and 8Bit Sample)154
PCM Operation155
PCM Initialization155
Audio Replay155
Audio Record156
Fifos Operation156
Data Flow Control157
Figure 7-6 Transmitting/Receiving FIFO Access Via APB Bus157
PCM Serial Clocks and Sampling Frequencies158
Interrupts158
Figure 7-7 PCMCLK and PCMSYN Generation Scheme158
Internal CODEC159
Overview159
Features159
Signal Descriptions160
Table 8-1 CODEC Signal IO Pin Description160
Block Diagram161
Figure 8-1 CODEC Block Diagram161
Figure 8-2 Internal CODEC Works with AIC161
Application Schematic162
Mapped Register Descriptions162
CODEC Internal Register Access Control (RGADW)163
Table 8-2 Internal CODEC Mapped Registers Description (AIC Registers)163
CODEC Internal Register Data Output (RGDATA)164
Operation164
Access to Internal Registers of the Embedded CODEC165
CODEC Controlling and Typical Operations165
Power Saving166
Pop Noise and the Reduction of It166
Timing Parameters167
C Parameters168
CODEC Internal Registers168
Registers Memory Map169
Register Description171
Programmable Gains202
Programmable Boost Gain: GIM202
Programmable Input Gain Amplifier: GID203
Programmable Digital Attenuation: GOD203
Programmable Attenuation: GO204
Programmable Digital Mixer Gain: GIMIX and GOMIX204
Gain Refresh Strategy205
Configuration of the Headphone Output Stage205
Out-Of-Band Noise Filtering206
Reset of Short Circuit Detection206
Sampling Frequency: FREQ206
Programmable Data Word Length207
Ramping System Note207
AGC System Guide208
AGC Operating Mode208
Figure 8-3 AGC Adjusting Waves209
DRC Description210
Figure 8-4 AGC Adjust Areas210
Digital Mixer Description211
Figure 8-5 Signal above Threshold at the Output of the Soft Clipping DRC211
Figure 8-6 Digital Mixer Structure211
Digital Microphone Interface212
Timing Diagram213
Timings213
Figure 8-7 Digital Microphone Interface Connection213
Figure 8-8 Digital Microphone Timing Diagram at MCLK = 12 Mhz (DMIC_CLK = 3 Mhz)213
Noise Template (TBC)214
Power Supply Noise Tolerance Template (PSNT2) on Analog Power Supply for I/O Buffers of DAC Outputs (VDDIO_CODEC)214
Figure 8-9 Digital Microphone Modulation Noise Reference Spectrum214
CODEC Operating Modes215
Figure 8-10 PSNT2 for VDDIO_CODEC When Using PWM Output215
Figure 8-11 PSNT2 for VDDIO_CODEC When Using PWM Output215
Initial All the Gain216
Figure 8-12 CODEC Power Diagram216
Soft Mute Mode217
Figure 8-13 ADC Gain up and Gain down Sequence217
Power-Down and Sleep Modes218
Figure 8-14 DAC Gain up and Gain down Sequence218
Working Modes Summary219
MCLK Turn-Off and Turn-On220
Requirements on Outputs and Inputs Selection and Power-Down Modes220
Initialization and Configuration220
Circuits Design Suggestions221
Avoid Quiet Ground Common Currents221
Figure 8-15 Peripheral Power Supply Connection221
Microphone Connection222
PCB Considerations224
Figure 8-16 Differential Routing224
Figure 8-17 PCB Optimization for Avoiding EMI Issue225
Analog Characteristics226
Operating Conditions226
With PWM Output, Used for Analog Amplifier Application226
Microphone / Line Input to ADC Path227
Table 8-3 Microphone/Line Input Performances228
Micbias and Reference229
I/O Buffers229
Table 8-4 I/O Buffer Static Characteristics229
Table 8-5 I/O Buffer Dynamic Characteristics229
Characteristics of the ADC High Pass Filter230
Characteristics of the ADC Wind Noise Filter230
Section 5 Memory Interface231
DDR Controller232
Overview232
Supported DDR SDRAM Types232
Block Diagram232
Register Description233
Table 9-1 DDRC Register233
Figure 9-1 DDR System Block Diagram233
Dstatus236
Dcfg238
Dctrl240
Dlmr243
DTIMING1,2,3,4,5,6 (DDR Timing Configure Register)244
DREFCNT (DDR Auto-Refresh Counter)248
DMMAP0,1 (DDR Memory Map Configure Register)249
DDLP (DDR DFI Low Power Handshake Control Register)250
DREMAP1,2,3,4,5 (DDR Address Remapping Register 1,2,3,4,5)250
WCMDCTRL1 (Performance Wcmd Reorder & Grouping)252
RCMDCTRL0 (Performance Rcmd Request Control)253
RCMDCTRL1 (Performance Rcmd Request Control)254
BOUNDARYSEL (Channel Boundary Select)255
WDATTHD0 (Performance Wcmd Request Control)257
WDATTHD1 (Performance Wcmd Request Control)257
IPORTPRI (Performance Priority Control)258
Chxqos0,1,2,3,4,5 (Performance Qos Control)259
Autosr_Cnt259
Autosr_En260
Clkstp_Cfg260
Ddrc_Status261
Phyret_Cfg261
Phyrst_Cfg262
Cpm_Drcg262
Functional Description263
DDRC and DDR2 Memory Initialization Sequence263
Change Clock Frequency264
Manually SELF-REFRESH Mode264
CPM Driven SELF-REFRESH Mode264
DLL Bypass Mode264
Data Endian265
Retention Flow265
Enter Retention Mode265
Exit Retention Mode266
SPI Flash Controller(SFC)270
Overview270
Features270
Block Diagram271
Functional Description271
Bus Function271
Figure 10-1 SFC Block Diagram271
Configurable Timing Parameter272
Figure 10-2 Sample Point(no Delay)272
Figure 10-3 Sample Point(Has Delay)272
Figure 10-4 AC Timing272
Pin Description273
Data Format Description273
Transfer Format273
Table 10-1 I/O Pin Description273
Figure 10-5 Data Format(Standard SPI)273
Figure 10-6 Data Format(Dual SPI)273
Endian Description274
Registers Description274
Instructions274
Figure 10-7 Data Format(Quad SPI)274
Map275
Table 10-2 SFC Registers Map275
Registers276
Software Guideline286
Phase Description286
Multi Phases Flow287
One Phase Flow287
Figure 10-8 Multi Phases Flow287
Meters of DMA Operation Need Attention288
Meters of Slave Mode Operation Need Attention288
Example (NAND Flash Write with Multi Phases in DMA Mode)288
Figure 10-9 One Phase Flow288
Example (NAND Flash Write with Single Phase in REG Mode)289
Index291
Table 10-3 Terms and Abbreviations291
Section 6 System Functions292
Clock Reset and Power Controller293
Overview293
CGU Block Diagram294
CGU Registers295
Table 7-2 Registers Memory Map-Address Base295
Table 11-2 CGU Registers Configuration295
PLL Operation320
Figure 11-1 Block Diagram of PLL321
Main Clock Division Change Sequence322
Power Manager322
Low-Power Modes and Function322
Register Description323
Table 11-3 Power/Reset Management Controller Registers Configuration323
IDLE Mode331
SLEEP Mode332
Reset Control Module332
Register Description332
Power on Reset333
WDT Reset333
Timer/Counter Unit334
Overview334
Pin Description334
Table 12-1 PWM Pins Description334
Register Description335
Table 11-1 Registers Memory Map-Address Base335
Table 12-3 TCU Registers Configuration335
Timer Control Register (TCSR)336
Timer Data FULL Register (TDFR)339
Timer Data HALF Register (TDHR)339
Timer Counter (TCNT)339
Timer Counter Enable Register (TER)340
Timer Counter Enable Set Register (TESR)341
Timer Counter Enable Clear Register (TECR)342
Timer Flag Register (TFR)343
Timer Flag Set Register (TFSR)343
Timer Flag Clear Register (TFCR)344
Timer Mast Register (TMR)345
Timer Mask Set Register (TMSR)346
Timer Mask Clear Register (TMCR)346
Timer Stop Register (TSR)347
Timer Stop Set Register (TSSR)348
Timer Stop Clear Register (TSCR)349
Timer Status Register (TSTR)350
Timer Status Set Register (TSTSR)351
Timer Status Clear Register (TSTCR)351
Operation352
Basic Operation in TCU1 Mode352
Disable and Shutdown Operation in TCU1 Mode353
Basic Operation in TCU2 Mode353
Disable and Shutdown Operation in TCU2 Mode353
Read Counter in TCU2 Mode353
Pulse Width Modulator (PWM)354
Trackball Input Waveform Detect354
Operating System Timer356
Overview356
Register Description356
Timer Clock Control Register (OSTCCR)357
Table 13-2 SYS_OST Registers Configuration357
Timer Counter Enable Register (OSTER, OSTESR, OSTECR)358
Timer Counter Clear Register (OSTCR)359
Timer Data FULL Register (OST1DFR)360
Timer Counter (OST1CNT)360
Timer Flag Register (OST1FR)360
Timer Mask Register (OST1MR)361
Operating System Timer Counter (OST2CNTH, OST2CNTL)361
Operating System Timer Counter High 32 Bits Buffer (OSTCNT2HBUF)361
Operation362
Basic Operation in Channel1362
Stop Operation in Channel1362
Modify the Prsecale in Channel1362
Interrupt Controller363
Overview363
Register Description363
Interrupt Controller Source Register (ICSR0)364
Table 12-2 Registers Memory Map-Address Base364
Table 14-2 INTC Register364
Interrupt Controller Source Register (ICSR1)365
Interrupt Controller Mask Register (ICMR0)365
Interrupt Controller Mask Register (ICMR1)366
Interrupt Controller Mask Set Register (ICMSR0)366
Interrupt Controller Mask Set Register (ICMSR1)366
Interrupt Controller Mask Clear Register (ICMCR0)367
Interrupt Controller Mask Clear Register (ICMCR1)367
Interrupt Controller Pending Register (ICPR0)367
Interrupt Controller Pending Register (ICPR1)368
Interrupt Source Register0 for PDMA (DSR0)368
Interrupt Mask Register0 for PDMA (DMR0)369
Interrupt Pending Register0 for PDMA (DPR0)369
Interrupt Source Register1 to PDMA (DSR1)369
Interrupt Mask Register1 for PDMA (DMR1)370
Interrupt Pending Register1 for PDMA (DPR1)370
Software Considerations371
Watchdog Timer372
Overview372
Register Description372
Watchdog Control Register (TCSR)373
Table 15-2 WDT Registers Configuration373
Watchdog Enable Register (TCER)374
Watchdog Timer Data Register (TDR)374
Watchdog Timer Counter (TCNT)375
Watchdog Timer Function375
PDMA Controller376
Overview376
Features376
Block Diagram376
Figure 16-1 Block Diagram of PDMA376
Memory Mapped Register Descriptions377
DMA Channel Registers377
Global Control Registers377
Table 13-1 Registers Memory Map-Address Base377
Table 16-2 DMA Channel Registers (N=0~31)377
Table 16-4 Global Control Registers377
DMA Channel Register Definition378
DMA Source Address (Dsan, N = 0 ~ 7)378
Table 14-1 Registers Memory Map-Address Base378
Table 16-3 Registers Memory Map-Address Base378
DMA Target Address (Dtan, N = 0 ~ 7)379
DMA Transfer Count (Dtcn, N = 0 ~ 7)379
DMA Request Types (Drtn, N = 0 ~ 7)379
DMA Channel Control/Status (Dcsn, N = 0 ~ 7)380
Table 16-5 Transfer Request Types380
DMA Channel Command (Dcmn, N = 0 ~ 7)381
Table 16-6 Available RDIL382
DMA Descriptor Address (Ddan, N = 0 ~ 7)384
DMA Stride Difference (Dsdn, N = 0 ~ 7)384
DMA Global Register Definition385
DMA Control385
DMA Interrupt Pending (DIRQP)386
DMA Doorbell (DDB)386
DMA Doorbell Set (DDS)387
Descriptor Interrupt Pending (DIP)387
Descriptor Interrupt Clear (DIC)387
DMA Channel Programmable (DMACP)388
DMA Soft IRQ Pending (DSIRQP)388
DMA Soft IRQ Mask (DSIRQM)389
DMA Channel IRQ Pending to MCU (DCIRQP)389
DMA Channel IRQ to MCU Mask (DCIRQM)390
Mcu390
MCU Control & Status390
MCU Normal Mailbox391
MCU Security Mailbox391
MCU Interrupt392
Multiple Bank Tightly Coupled Sharing Memory392
CP0 Registers of MCU392
Table 16-7 TCSM Space392
Normal Exceptions Accepted by MCU393
How to Boot MCU up393
DMA Manipulation394
Descriptor Transfer Mode394
Table 16-8 Descriptor Structure395
Figure 16-2 Descriptor Transfer Flow396
Descriptor Transfer Mode397
Descriptor Transfer Interrupt/Stop Control397
Figure 16-3 Example for Stride Transfer Mode397
DMA Requests399
Auto Request399
On-Chip Peripheral Request399
How to Use Programmable DMA Channel399
Real Time Clock400
Overview400
Features400
Block Diagram400
Pins Description401
Registers Description401
Table 15-1 Registers Memory Map-Address Base402
Table 17-1 Registers Memory Map-Address Base402
Table 17-2 Registers for Real Time Clock402
Table 17-3 Registers for Hibernating Mode402
RTC Control Register (RTCCR)403
RTC Second Register (RTCSR)404
RTC Second Alarm Register (RTCSAR)405
RTC Regulator Register (RTCGR)405
Hibernate Control Register (HCR)406
HIBERNATE Mode Wakeup Filter Counter Register (HWFCR)406
Hibernate Reset Counter Register (HRCR)407
HIBERNATE Wakeup Control Register (HWCR)407
HIBERNATE Wakeup Status Register (HWRSR)408
Hibernate Scratch Pattern Register (HSPR)409
Write Enable Pattern Register (WENR)410
WKUP_PIN_RST Control Register (WKUPPINCR)410
Operation Flow411
Registers Access411
Normal Mode412
HIBERNATE Mode412
Figure 17-1 Core Power on412
Time Regulation413
Clock Select413
Table 17-4 Clock Select Registers414
Figure 17-2 RTC Clock Selection Path414
EFUSE Slave Interface (EFUSE)415
Overview415
Registers415
Registers Memory Map416
Registers and Fields Description416
Table 16-1 Registers Memory Map-Address Base416
Flow420
Program EFUSE Flow420
Program Security Key Flow421
Read EFUSE Flow421
Read Security Key/Random Number Flow421
General-Purpose I/O Ports423
Overview423
Features423
About GPIO Port Summary Table423
Table 19-1 GPIO Port Summary Table Illustration423
GPIO Port a Summary424
Table 19-2 GPIO Port a Summary424
GPIO Port B Summary425
Table 19-3 GPIO Port B Summary425
GPIO Port C Summary426
GPIO Port D Summary426
GPIO Port Z - Shadow Group426
Table 19-4 GPIO Port C Summary426
Table 19-5 GPIO Port D Summary426
Registers Description427
Table 19-6 Registers Memory Map-Address Base427
Table 19-7 GPIO Registers428
PORT a Register Group430
PORT B Register Group438
PORT C Register Group445
PORT D Register Group458
PORT Z Shadow Register Group466
GPIOZ Group ID to Load Register (Pzgid2Ld,0Xf0)468
Program Guide469
Port Function Guide469
Configure Without 3Rd-Unexpected State469
SMB Controller471
Overview471
Features471
Pin Description471
Table 20-1 SMB Pin Description471
Registers472
Registers Memory Map472
Table 20-2 Registers Memory Map-Address Base472
Table 20-3 Registers Memory Map-Address Offset472
Registers and Fields Description473
Operating Flow497
SMB Behavior498
Master Mode Operation498
Slave Mode Operation500
Disabling SMB503
Summary the Condition Could Flush TX FIFO504
The Condition Could Generate START, STOP and RESTART504
Figure 20-1 Master Transmitter - Tx FIFO Empties/Stop Generation504
Figure 20-2 Master Receiver - Tx FIFO Empties/Stop Generation505
Figure 20-3 Master Transmitter - Restart Bit of SMB_DC Is Set505
Figure 20-4 Master Receiver - Restart Bit of SMB_DC Is Set505
Figure 20-5 Master Transmitter - Stop Bit of SMB_DC Set/Tx FIFO Not Empty506
Figure 20-6 Master Transmitter - First Byte Loaded into Tx FIFO Allowed to Empty, Restart Bit506
Figure 20-7 Master Receiver - Stop Bit of IC_DATA_CMD Set/Tx FIFO Not Empty506
Figure 20-8 Master Receiver - First Command Loaded after Tx FIFO Allowed to Empty/Restart507
Smart Card Controller508
Overview508
Pin Description509
Register Description509
Table 21-1 Smart Card Controller Pins Description509
Table 21-2 Smart Card Controller Registers Description509
Transmit/Receive FIFO Data Register (SCCDR)510
FIFO Data Count Register (SCCFDR)510
Control Register (SCCCR)510
Status Register (SCCSR)512
Transmission Factor Register (SCCTFR)512
Extra Guard Timer Register (SCCEGTR)513
ETU Counter Value Register (SCCECR)513
Reception Timeout Register (SCCRTOR)513
Synchronous Serial Interface(SSI)514
Overview514
Features514
Block Diagram515
Functional Description515
Figure 22-1 SSI Block Diagram515
Pin Description516
Data Formats516
Table 22-1 SSI Controller Pins Description516
Motorola's SPI Format Details517
Figure 22-2 SPI Single Character Transfer Format (PHA = 0)517
Figure 22-3 SPI Single Character Transfer Format (PHA = 1)517
Figure 22-4 SPI Back-To-Back Transfer Format518
Figure 22-5 SPI Frame Interval Mode Transfer Format (ITFRM = 0, LFST = 0)519
Ti's SSP Format Details520
Figure 22-6 SPI Frame Interval Mode Transfer Format (ITFRM = 1, LFST = 1)520
Figure 22-7 Ti's SSP Single Transfer Format520
National Microwire Format Details521
Figure 22-8 Ti's SSP Back-To-Back Transfer Format521
Figure 22-9 National Microwire Format 1 Single Transfer522
Figure 22-10 National Microwire Format 1 Back-To-Back Transfer522
Figure 22-11 National Microwire Format 2 Read Timing522
Register Description523
Register Mapping523
Figure 22-12 National Microwire Format 2 Write Timing523
SSI Data Register (SSIDR)524
Table 22-2 SSI Serial Port Registers524
SSI Control Register0 (SSICR0)525
SSI Control Register1 (SSICR1)527
SSI Status Register (SSISR)529
SSI Interval Time Control Register (SSIITR)530
SSI Interval Character-Per-Frame Control Register (SSIICR)531
SSI Clock Generator Register (SSIGR)531
SSI Receive Counter Register (SSIRCNT)532
Software Guideline532
Common Flow532
Interrupt Operation533
Index533
Table 22-3 SSI Interrupts533
Universal Asynchronous Receiver/Transmitter(Uart)535
Overview535
Features535
Block Diagram535
Figure 23-1 UART DATA Controller Block Diagram535
Functional Description536
Full-Duplex Operation536
The Meaning of All Bits536
RFIFO and TFIFO536
Transmission, Reception and Line Status Independently536
Slow Infrared Asynchronous Interface536
Pins Description536
Table 23-1 UART Pins Description536
Data Format Description537
Register Description537
Register Memory Map537
Table 23-2 Registers Memory Map Base Address537
Figure 23-2 UART Frame Structure Diagram537
Register and Fields Description538
Table 23-3 UART Registers Map538
Table 23-4 UART Interrupt Identification Register Description542
Operation Flow552
UART Configuration552
Data Transmission552
Data Reception552
Receive Error Handling553
Modem Transfer553
DMA Transfer553
Slow Irda Asynchronous Interface553
For any Frequency Clock to Use the UART554
Index556
Table 23-5 Description of Proprietary Vocabulary556
MMC/SD CE-ATA Controller（Msc557
Overview557
Features557
Block Diagram558
Functional Description558
Figure 24-1 MMC/SD Controller Block Diagram558
MSC Reset559
Voltage Validation559
Card Registry559
Card Access560
Protection Management562
Table 24-1 Command Data Block Structure563
Card Status565
Table 24-2 Card Status Description566
SD Status569
Sdio569
Table 24-3 SD Status Structure569
Clock Control571
Application Specified Command Handling571
Pins Description571
Data Format Description572
Register Description572
Figure 24-2 Msc Data Format572
Register Memory Map573
Table 24-4 Registers Memory Map Base Address573
Table 24-5 MSC Registers Map573
Register and Fields Description574
Operation Flow594
Data Fifos594
DMA and Program I/O594
Start and Stop Clock596
Software Reset597
Voltage Validation and Card Registry597
Single Data Block Write599
Single Block Read600
Multiple Block Write600
Multiple Block Read601
Table 24-6 How to Stop Multiple Block Write601
Table 24-7 How to Stop Multiple Block Read601
Stream Write (MMC)602
Stream Read (MMC)603
Erase, Select/Deselect and Stop603
SDIO Suspend/Resume604
SDIO Read Wait604
Operation and Interrupt604
Index605
Table 24-8 Description of Proprietary Vocabulary605
Table 24-9 the Mapping between Commands and Steps605
OTG Controller607
Overview607
Block Diagram608
Slave-Only Mode608
Internal DMA Mode608
Pin Description608
Table 25-1 OTG Pins Description608
Figure 25-1 OTG Slave-Only Mode608
Figure 25-2 OTG Internal DMA Mode608
Register Map609
CSR Memory Map609
Register Maps609
Table 25-2 Registers Memory Map Base Address609
Figure 25-3 OTG CSR Memory Map609
Global CSR Map610
Table 25-3 Core Global CSR Map (000H-3Ffh)610
Host Mode CSR Map611
Device Mode CSR Map611
Table 25-4 Host Mode CSR Map (400H-7Ffh)611
Table 25-5 Device Mode CSR Map (800H-Bffh)611
Data FIFO (DFIFO) Access Register Map613
Table 25-6 Data FIFO (DFIFO) Access Register Map613
Register Descriptions614
Application Access to the Csrs614
Overview of Commonly Used Register Bits615
Table 25-7 List of Commonly Used Register Bits615
Global Registers619
Table 25-8 Control and Status Register: GOTGCTL619
Table 25-9 Interrupt Register: GOTGINT623
Table 25-10 AHB Configuration Register: GAHBCFG624
Table 25-11 USB Configuration Register: GUSBCFG628
Table 25-12 Reset Register: GRSTCTL633
Table 25-13 Interrupt Register: GINTSTS636
Table 25-14 Interrupt Mask Register: GINTMSK643
Table 25-15 Host Mode Receive Status Debug Read/Status Read and Pop Registers645
Table 25-16 Device Mode Receive Status Debug Read/Status Read and Pop Registers645
Table 25-17 Receive FIFO Size Register: GRXFSIZ646
Table 25-18 Non-Periodic Transmit FIFO Size Register: GNPTXFSIZ647
Table 25-19 Non-Periodic Transmit FIFO Size Register: GNPTXFSIZ647
Table 25-20 Non-Periodic Transmit Fifo/Queue Status Register: GNPTXSTS647
Table 25-21 User HW Config1 Register: GHWCFG1648
Table 25-22 User HW Config2 Register: GHWCFG2649
Table 25-23 User HW Config3 Register: GHWCFG3651
Table 25-24 User HW Config4 Register: GHWCFG4653
Table 25-25 Global DFIFO Software Config Register: GDFIFOCFG655
Table 25-26 Host Periodic Transmit FIFO Size Register: HPTXFSIZ656
Table 25-27 Device Periodic Transmit FIFO-N Register: Dptxfsizn656
Host Mode Registers657
Table 25-28 Device in Endpoint Transmit FIFO Size Register: (Dieptxfn)657
Table 25-29 Host Configuration Register: HCFG658
Table 25-30 Host Frame Interval Register: HFIR660
Table 25-31 Host Frame Number/Frame Time Remaining Register: HFNUM661
Table 25-32 Host Periodic Transmit Fifo/Queue Status Register: HPTXSTS661
Table 25-33 Host All Channels Interrupt Register: HAINT662
Table 25-34 Host All Channels Interrupt Mask Register: HAINTMSK662
Table 25-35 Host Port Control and Status Register: HPRT663
Table 25-36 Host Channel-N Characteristics Register: Hccharn666
Table 25-37 Host Channel-N Split Control Register: Hcspltn668
Table 25-38 Host Channel-N Interrupt Register: Hcintn669
Table 25-39 Host Channel-N Interrupt Mask Register: Hcintmskn671
Table 25-40 Host Channel-N Transfer Size Register: Hctsizn672
Table 25-41 Host Channel-N DMA Address Register: Hcdman674
Device Mode Registers675
Table 25-42 Host Channel-N DMA Buffer Address Register: Hcdmabn675
Table 25-43 Host Frame List Base Address Register: Hflbaddr675
Table 25-44 Device Configuration Register: DCFG676
Table 25-45 Device Control Register: DCTL678
Table 25-46 Minimum Duration for Soft Disconnect682
Table 25-47 Device Status Register: DSTS682
Table 25-48 Device in Endpoint Common Interrupt Mask Register: DIEPMSK684
Table 25-49 Device out Endpoint Common Interrupt Mask Register: DOEPMSK684
Table 25-50 Device All Endpoints Interrupt Register: DAINT685
Table 25-51 Device Endpoints Interrupt Mask Register: DAINTMSK686
Table 25-52 Device in Token Sequence Learning Queue Read Register 1: DTKNQR1686
Table 25-53 Device in Token Sequence Learning Queue Register 2: DTKNQR2687
Table 25-54 Device in Token Sequence Learning Queue Register 3: DTKNQR3687
Table 25-55 Device in Token Sequence Learning Queue Register 4: DTKNQR4687
Table 25-56 Device VBUS Discharge Time Register: DVBUSDIS688
Table 25-57 Device VBUS Pulsing Time Register (DVBUSPULSE)688
Table 25-58 Device Threshold Control Register (DTHRCTL)689
Table 25-59 Device in Endpoint FIFO Empty Interrupt Mask Register: DIEPEMPMSK690
Table 25-60 Device each Endpoint Interrupt Register: DEACHINT691
Table 25-61 Device each Endpoint Interrupt Register Mask: DEACHINTMSK691
Table 25-62 Device each in Endpoint-N Interrupt Register: Diepeachmskn692
Table 25-63 Device each out Endpoint-N Interrupt Register: Doepeachmskn693
Table 25-64 Device Control in Endpoint 0 Control Register: DIEPCTL0693
Table 25-65 Device out Endpoint 0 Control Register: DOEPCTL0695
Table 25-66 Device Endpoint-N Control Register: Diepctln/Doepctln697
Table 25-67 Device Endpoint-N Interrupt Register: Diepintn/Doepintn701
Table 25-68 Device in Endpoint 0 Transfer Size Register: DIEPTSIZ0704
Table 25-69 Device out Endpoint 0 Transfer Size Register: DOEPTSIZ0705
Table 25-70 Device Endpoint-N Transfer Size Register: Dieptsizn/Doeptsizn705
Table 25-71 Device Endpoint-N DMA Address Register: Diepdman/Doepdman707
Table 25-72 Device Endpoint-N DMA Buffer Address Register: Diepdmabn/Doepdmabn707
Operation Flow708
Core Initialization708
Table 25-73 Device in Endpoint Transmit FIFO Status Register: Dtxfstsn708
Programming the Device Core709
Programming the Host Core712
Mac714
Features714
Section 8 Boot715
Xburst Boot ROM Specification716
Boot Select716
Boot Procedure716
Table 27-1 Boot Configuration of X1000716
Figure 27-1 Boot Sequence Diagram of X1000717
SPL Structure718
SPL Paramaters718
Figure 27-2 the Basic SPL Structure718
Table 27-2 SPL Parameters Structure719
Figure 27-3 SPL Parameters Location719
Figure 27-4 SPL Configuration Change Procedure721
USB Boot Specification722
Table 27-3 Transfer Types Used by the Boot Program722
Figure 27-5 USB Communication Flow722
Figure 27-6 Typical Procedure of USB Boot724
Table 27-4 Vendor Request 0 Setup Command Data Structure725
Table 27-5 Vendor Request 1 Setup Command Data Structure725
Table 27-6 Vendor Request 2 Setup Command Data Structure725
Table 27-7 Vendor Request 3 Setup Command Data Structure725
MSC0 Boot Specification726
Table 27-8 Vendor Request 4 Setup Command Data Structure726
Table 27-9 Vendor Request 5 Setup Command Data Structure726
Figure 27-7 Typical Procedure of MSC0 Boot727
MSC1 Boot Specification728
SFC Boot Specification728
Figure 27-8 SPL Structure of MSC0/MSC1 Boot728
Figure 27-9 X1000 SPI Boot Procedure729
Table 27-10 SPI nor Flash Boot Flag Informations(in Spl Signature)730
Table 27-11 SPI NAND Flash Boot Flag Informations(in Spl Signature)730

Brand	Ingenic
Model	X1000
Category	Computer Hardware
Language	English

Ingenic X1000 User Manual

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Ingenic X1000 Specifications

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