MMC/SD CE-ATA Controller（MSC）
X1000 IoT Application Processor Programming Manual
Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
MSC_DMAC.AOFST
Step 3: Write the descriptor address to MSC_DMANDA
Step 4: Configure MSC controller to read or write operation, e,g, set MSC_NOB, MSC_BLEN and
MSC_CMDAT.WRITE_READ etc.
Step 5: If DMAEND interrupt is wanted, clear MSC_IMASK.DMAEND, otherwise, set this bit
Step 6: Select SDMA by setting MSC_DMAC.DMASEL to 0b
Step 7: Start DMA transfer by setting MSC_DMAC.DMAEN
Step 8: Waiting the DMAEND interrupt (if interrupt is used) or status (if interrupt is not used)
Step 9: Disable the SDMA by configuring MSC_DMAC.DMAEN to 0b
24.8.2.3 Operation of CDMA
To access MSC_RXFIFO/MSC_TXFIFO with the DMA, the software must program the DMA to read or
write the FIFO with source port width 32-bit, destination port width 32-bit, transfer data size 32-byte,
transfer mode single. For example, to write 64 bytes of data to the MSC_TXFIFO, the software must
program the DMA as follows:
DMA_DCTRn = 2 // Write 2 32-bytes (64 bytes)
DMA_DCCRn[SWDH] = 0 // source port width is 32-bit
DMA_DCCRn[DWDH] = 0 // destination port width is 32-bit
DMA_DCCRn[DS] = 4 // transfer data size is 32-byte
DMA_DCCRn[TM] = 4 // transfer mode is single
DMA_DCCRn[RDIL] = 0 // request detection interval length is 0
The number of 32-bytes should be calculated from the number of transferred bytes as follows:
The number of words = (The number of bytes + 31) / 32
If the number of transferred bytes is not the multiple of 4, the controller can correctly process endian.
The DMA trigger level is 8 words, that is to say, the DMA read trigger is when data words in
MSC_RXFIFO is >= 8 and the DMA write trigger is when data words in MSC_TXFIFO is < 8. Software
can also configure DMA registers based on requirements, but the above 32-byte transfer data size is
most efficient.
24.8.2.4 Operation of Program I/O
With program I/O, the software waits for the MSC_IFLG [RXFIFO_RD_REQ] or MSC_IFLG
[TXFIFO_WR_REQ] interrupts before reading or writing the respective FIFO.
NOTES:
1 The MSC_CMDAT [DMA_EN] bit must be set to a 1 to enable communication with the DMA
and it must be set to a 0 to enable program I/O.
2 DMA can be enabled only after MSC_CMDAT is written, because MSC_CMDAT [DATA_EN]
is used to reset TX/RXFIFO.
24.8.3 Start and Stop clock
The software stops the clock as follows:
1 Write MSC_CTRL with 0x01 to stop the MMC/SD bus clock.
2 Wait until MSC_STAT[CLK_EN] becomes zero.
To start the clock the software writes MSC_CTRL with 0x02.
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