Ingenic X1000 - Ddrc_Status; Phyret_Cfg

DDR Controller
233
X1000 IoT Application Processor Programming Manual
Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
[30]
idle_cond_en
Enable judge condition: ddrc idle
[29]
lp_cond_en
Enable judge condition: low-power mode (DCTRL.PDT)
0x0
[28]
sr_cond_en
Enable judge condition: self-refresh
0x0
[11:0]
dly_timer
Specify the time before shutting down the clock after all
condition met.
0x20
Please Note that:
The CLKSTP will affect the function of lp(low power mode), auto-sr(auto self-refresh)mode. If the
Clock is gating, the timer used for lp/auto-sr will stop running. As a result, if the Auto-self-refresh
enabled, the bit [28] should be set.
9.2.21 DDRC_STATUS
Description:
Read-Only register indicates the ddrc status. This register can be accessed even in DDR retention
mode.
DDRC_STATUS
0xB301206C
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
ckc_reject
ckc_ack
ckc_req
Reserved
ddr_sr_mode
ddr_lp_mode
ddrc_idle
ch6_bus_idle
ch5_bus_idle
ch4_bus_idle
ch3_bus_idle
ch2_bus_idle
ch1_bus_idle
ch0_bus_idle
Reserved
clkstp_req
RST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
Rrset
[13]
ddr_sr_mode
0: DRAM is not in self-refresh mode
1: DRAM is in self-refresh mode
0
[12]
ddr_lp_mode
0: ddr PHY is not in low-power mode
1: ddr PHY is in low-power mode
0
[11]
ddrc_idle
Indicates the ddrc control logic is idle
1
[10:4]
chx_bus_idle
Indicates the bus interface for each channel is idle
1
[3:1]
Reserved
0
[0]
clkstp_req
Indicates the ddrc is requiring CPM gating ddrc clock
0
9.2.22 PHYRET_CFG
Description:
DDR PHY can be set into retention mode, which allow power cutting-down. This can save the
leakage power in highest level.
However, when use this function, please flow the retention flow.