Intel 80386 - Page 11

TABLE OF CONTENTS
Page
8.3 Basic I/O Interface ......................................................................................... 8-4
8.3.1 Address Latch ..................... ....................................................................... 8-5
8.3.2 Address Decoder ....................................................................................... 8-6
8.3.3 Data Transceiver ......................................................................... ...... ......... 8-8
8.3.4 Bus
Control Logic ................................................... ................................... .8-8
8.4 Timing Analysis for I/O Operations ................................................................ 8-9
8.5 Basic
I/O Examples ............................................... ........................................ 8-13
8.5.1 8274 Serial Controller .................................................................................. 8-14
8.5.2 8259A
Interrupt Controller ........................... ............................................... 8-14
8.5.2.1
Single Interrupt Controller ....................................................................... 8-15
8.5.2.2 Cascaded
Interrupt Controllers ............................................................... 8-16
8.5.2.3
Handling More Than 64 Interrupts ........................................................... 8-16
8.6
80286-Compatible Bus Cycles .............................. ........................................ 8-16
8.6.1
AO/A1 Generator ........................................................................................ 8-17
8.6.2
SO#/S1# Generator .................................................................................. 8-17
8.6.3 Wait-State Generator ............ ..................................................................... 8-18
8.6.4 Bus
Controller and Bus Arbiter .................................................................. 8-19
8.6.5 82258 ADMA
Controller ..........................................................................•. , 8-20
8.6.5.1 82258 as Bus Master .............................................................................. 8-22
8.6.5.2 82258 as
Peripheral ................................................................................ 8-24
8.6.6 82586 LAN Coprocessor ............................................................................ 8-25
8.6.6.1 Dedicated
CPU ........................................ ... .......... ................................... 8-26
8.6.6.2
Decqupled Dual-Port Memory ................................................................. 8-26
8.6.6.3
Coupled Dual-Port Memory ..................................................................... 8-27
8.6.6.4
Shared Bus ............................................................................................. 8-28
CHAPTER 9
MUL TIBUS® I AND 80386
9.1 MUL TIBUS® I (IEEE 796) ............... ................................................................ 9-1
9.2 MUL TIBUS® I Interface Example ......................................................... .......... 9-2
9.2.1 Address Latches and Data Transceivers .................................................... 9-2
9.2.2 Address Decoder ....................................................................................... 9-5
9.2.3 Wait-State Generator ................................................................................. 9-5
9.2.4 Bus
Controller and Bus Arbiter .................................................................. 9-7
9.3 Timing
Analysis of MUL TIBUS® I Interface .................................................... 9-10
9.4 82289 Bus Arbiter .................................................................... ....... .............. 9-10
9.4.1 Priority Resolution .....•......................................................................... ....... 9-11
9.4.2 82289 Operating Modes ............................................................................ 9-11
9.4.3 MULTIBUS® I Locked Cycles ............................................................ \........ 9-14
9.5 Other
MULTIBUS® I Design Considerations ............................... ,.................. 9-14
9.5.1
Interrupt-Acknowledge on MUL TIBUS® I .................................................... 9-14
9.5.2 Byte Swapping during MUL
TIBUS® I Byte Transfers ................................. 9-16
9.5.3 Bus Timeout Function for
MULTIBUS® I Accesses .................................... 9-17
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