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General| Clock Speed | 12 MHz to 40 MHz |
|---|---|
| Transistor Count | 275, 000 |
| Addressable Memory | 4 GB |
| Data Bus Width | 32-bit |
| Instruction Set | x86 |
| Introduction Date | October 17, 1985 |
| Virtual Memory | Yes |
| Operating Modes | Real mode, Protected mode, Virtual 8086 mode |
| Manufacturer | Intel |
| Model | 80386 |
| Address Bus Width | 32-bit |
| Voltage | 5V |
| Manufacturing Process | 1.5 µm |
| Cache | No on-chip cache |
| FPU | Optional (80387) |
| Bus Interface | 32-bit |
| Process Technology | CHMOS III |
| Package | PGA |
Details the 80386 microprocessor's performance, architecture, and features.
Explains the 80386's numeric coprocessor interface for the 80287 and 80387.
Describes the 80386's interface to its environment, handling requests and signals.
Details the seven types of bus operations performed by the 80386.
Covers address pipelining for overlapping bus cycles to increase throughput.
Details non-pipelined and pipelined address read cycles and their timing.
Explains non-pipelined and pipelined address write cycles and their timing.
Describes how NA# controls address pipelining to overlap bus cycles.
Details timing requirements for read cycles, write cycles, and READY# signal.
Discusses hardware and software interrupts affecting 80386 execution.
Explains the HOLD/HLDA protocol for bus control transfer to other bus masters.
Details the RESET signal's function, timing, and effect on 80386 states.
Discusses techniques like wait states and address pipelining to improve system performance.
Details the connections and bus cycles for interfacing the 80287 coprocessor.
Explains the synchronous and pseudosynchronous interface for the 80387 coprocessor.
Discusses the trade-offs between memory speed, system performance, and cost.
Explains cache fundamentals, program locality, and block fetch concepts.
Details fully associative, direct mapped, and set associative cache organizations.
Compares I/O mapping and memory mapping for I/O devices and protection features.
Details timing requirements for devices using the basic I/O interface.
Introduces the MULTIBUS II standard, its architecture, and specialized buses.
Addresses reflections, interference, and noise in high-frequency signal paths.
Outlines an incremental approach to building and debugging 80386 hardware.
Details automatic self-test and Translation Lookaside Buffer (TLB) testing features.
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