CHAPTER 4
PERFORMANCE
CONSI[)ERAT~ONS
System performance measures
how
fast a microprocessing system performs a given task or
set of instructions. Through increased processing speed and data throughput, an
80386
operating at the heart of a system can improve overall performance immensely. The design
of supporting logic and devices for efficient interaction with the
80386
is
also important in
optimizing system performance.
This chapter describes considerations for achieving high performance
in
80386-based systems.
A variety
of
examples illustrate the potential performance levels for a number of
applications.
4.1 WAIT STATES AND PIPELINING
Because a system may include devices whose response
is
slow
relative to the 80386 bus cycle,
the overall system performance
is
often less than the potential performance of the 80386.
Two techniques for accommodating slow devices are wait states and address pipelining. The
designer must consider how to use one or both of these techniques to minimize the impact
of device performance
on
system performance.
The impact of memory device speed on performance
is
generally much greater than
that
of
I/O
device speed because most programs require more memory accesses than
I/O
accesses.
Therefore, the following discussion focuses on memory performance.
Wait states are extra
eLK
cycles added to the 80386 bus cycle. External logic generates
wait states by delaying the READY
# input to the 80386. For an 80386 operating
at
16
MHz, one wait state adds 62.5 nanoseconds to the time available for the memory to respond.
Each wait state increases the bus cycle time by
50 percent of the zero wait-state cycle time;
however, overall system performance does not vary in direct proportion to the bus cycle
increase. The second column of Table
4-1
shows the performance impact (based on an
example simulation) for memory accesses requiring different numbers of wait states; one
wait state results in an overall performance decrease of
19
percent.
Table
4-'1.
80386
Performance
with
Wait
States
and
Pipelining
Wait
States
Wait
States
Performance
Relative
Bus
When
Address
When
Address
to
Non-Pipelined
Utilization
is
Pipelined
is
Not
Pipelined
o Wait-State
0 0 1.00 73%
0 1
0.91
79%
1 1
0.81
86%
1 2
0.76 89%
2 2 0.66
91%
2
3 0.63 92%
3 3 0.57 93%
4-1
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