PERFORMANCE CONSIDERATIONS
Unlike a wait state, address pipelining increases the time that a memory has to respond by
one CLK cycle without lengthening the bus cycle. This extra CLK cycle eliminates the output
delay of the
80386 address and status outputs. Address pipelining overlaps the address and
status outputs of the next bus cycle with the end of the current bus cycle, lengthening the
address access time by one or more CLK cycles from the point of
view
of the accessed
memory device. An access that requires two wait states without address pipelining would
require one wait state with address pipelining. The third column of Table
4-1
shows
performance with pipelining for different wait-state requirements.
Address pipelining
is
advantageous for most bus cycles, but if the next address
is
not avail-
able before the current cycle ends,the
80386 cannot pipeline the next address, and the bus
timing
is
-identical to a non-pipelined bus cycle. Also, the first bus cycle after an idle bus
must always be non-pipelined because there
is
no
previous cycle in which to output the address
early.
If
the next cycle
is
to be pipelined, the first cycle must be lengthened by
at
least one
wait state
so
that the address can be output before the end of the cycle.
With the
80386, address pipelining
is
optional
so
that bus cycle timing can be closely tailored
to the access time of the memory device; pipelining can be activated once the address is
latched externally or not activated if the address
is
not latched.
The
80386 NA# input controls address pipelining. When the system
no
longer requires the
80386 to drive the address of the current bus cycle (in most systems, when the address has
been latched), the system can activate the
80386 NA# input. The 80386 outputs the address
and status signals for the next bus cycle
on
the next CLK cycle.
The system must activate the NA# signal without knowing which device the next bus cycle
will access. In an optimal
80386 system, address pipelining should be used
even
for fast
memory
that
does
not require pipelining, because if a fast memory access
is
followed by a
pipelined cycle to slower memory, one wait state
is
saved.
If
a fast memory access
is
followed
by another fast memory access, the extra time
is
not used, and
no
processor time
is
lost.
Therefore, all devices in a system must be able to accept both pipelined and non-pipelined
cycles.
Consider a system in which a non-pipelined memory access requires one wait state and a
non-pipelined
I/O
access requires four wait states. The bus control logic reads chip select
signals from the address decoder to determine whether one or four wait states are required
for the bus cycle. The bus control logic also determines whether the address has been
pipelined, because a pipelined cycle requires one less wait state. The system includes logic
for generating a Bus Idle signal that indicates whether the bus cycle has ended. The bus
control logic can therefore detect that the address has been pipelined if the Address Status
(ADS#) signal goes active while the Bus Idle signal
is
inactive.
Address pipelining
is
less effective for
I/O
devices requiring several wait states. The larger
the number of wait states required, the less significant the elimination of one wait state
through pipelining,becomes. This fact coupled with the relative infrequency of
I/O
accesses
means that address pipelining for
I/O
devices usually makes little difference to system
performance.
4-2
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