CACHE SUBSYSTEMS
-
OTHER
BUS
MASTER
~
"OO"~
~
}
NON.CACHEABlE
---------
)
80386
CACHE
I--
MEMORY
CACHEABlE
G30107
Figure 7-8. Non-Cacheable Memory
7.4
EFFICIENCY
AND
PERFORMANCE
The measurement of cache effectiveness
is
divided into two topics: efficiency and perform-
ance. Cache efficiency
is
its ability to maintain the most used code and data requested by
the microprocessor. Efficiency
is
measured
in
terms of hit rate. Performance
is
a measure-
. ment of the speed in which a microprocessor can perform a given task, and
is
measured in
effective waitstates.
Hit
rate
is
but one of many factors which affect performance. Write
policy, update policy, and coherency methods are performance factors
as
well.
Hit rate data for various cache organizations
is
shown
in
Table 7-1. These statistics were
computed by analyzing several mainframe traces, and selecting the one which produced the
lowest hit rate. Thus, the numbers listed are a conservative estimate of cache efficiency.
Note that hit rate statistics are not absolute quantities. The hit rate of a particular cache
implementation can vary widely depending
on
software. Therefore, Table
7-1
should only be
used to compare one cache configuration against another listed. The relative hit rates should
be weighed against other considerations, such as hardware complexity,
in
selecting a cache
organization.
7.5
CACHE
AND
DMA
Cache coherency
is
an issue one must consider when placing a DMA controller in an 80386
system. Because the DMA controller has access to main memory, it can potentially intro-
duce stale data. Stale data can be avoided
in
the following
ways:
• Implementing bus watching (snooping). In this approach, the DMA controller writes to
main memory, and the cache controller monitors
DMA
cycles and automatically invali-
dates any cache location altered by DMA.
7-12
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