Intel 80386

LOCAL BUS INTERFACE
The following pins are used to control the execution of instructions in the 80386 and to
interface external bus masters. The 80386 provides both a standard interface to communi-
cate with other bus masters and a special interface support a numerics coprocessor.
• The CLK2 input provides a double-frequency clock signal for synchronous operation. This
signal
is divided by two internally, so the 80386 fundamental frequency is half the CLK2
signal frequency. For example, a 20-MHz 80386 uses a 40-MHz CLK2 signal.
• The RESET input forces the 80386 to a known reset state.
• The HOLD signal can be generated by another bus master to request that the 80386
release control of the bus. The 80386 responds
by activating the Hold Acknowledge
(HLDA) signal
as it relinquishes control of the local bus.
• The Maskable Interrupt (INTR) and Non-Maskable Interrupt (NMI) inputs cause the
80386 to interrupt its current instruction stream and begin execution of an interrupt service
routine.
• The BUSY #, ERROR#, and Coprocessor Request (PEREQ) signals make up the inter-
face to an external numeric coprocessor.
BUSY # and ERROR# are status signals from
the coprocessor;
PEREQ allows the coprocessor to request data from the 80386. The
80386 can use either the 80287 or the 80387 coprocessor.
All of the 80386 bus interface pins are summarized
in Table 3-1.
3.1 BUS OPERATIONS
There are seven types of bus operations:
• Memory read
• Memory write
• I/O read
• I/O write
• Instruction fetch
• Interrupt acknowledge
• Halt/shutdown
Each bus cycle
is initiated when the address is valid on the address bus, and bus status pins
are driven to states that correspond to the type of bus cycle, and ADS# is driven
low. Status
pin states that correspond to each bus cycle type are shown
in Table 3-2. Notice that the
signal combinations marked as invalid states may occur when ADS#
is false (high). These
combinations will never occur if the signals are sampled
on the CLK2 rising edge when
ADS#
is low, and the 80386 internal CLK is high (as indicated by the CLK output of the
82384). Bus status signals must be qualified with ADS#
is true (low) to identify the bus
cycle.
Memory read and memory write cycles can be locked to prevent another bus master from
using the local bus and allow for indivisible read-modify-write operations.
3-2