1/0
INTERFACING
8259As, called slave controllers. The interface between the 80386 and multiple cascaded
8259As
is
an extension of the single-8259A interface with the following additions:
• The cascade address outputs (CAS2#-CASO#) are output to provide address and chip-
select signals for the slave controllers.
• The interrupt request lines (IR7-IRO) of the master controller are connected to the
INT
outputs of the slave controllers.
Each slave controller resolves priority between up to eight interrupt requests and transmits
a single interrupt request to the master controller. The master controller,
in
turn, resolves
interrupt priority between up to eight slave controllers and transmits a single interrupt request
to the
80386.
The timing of the interface
is
basically the same
as
that of a single 8259A. During the first
interrupt-acknowledge cycle, all the 8259As freeze the states of their interrupt request inputs.
The master controller outputs the cascade address to select the slave controller that
is
gener-
ating the request with the highest priority. During the second interrupt-acknowledge cycle,
the selected slave controller outputs an interrupt vector to the
80386.
Chapter 9 describes the interface to slave controllers that reside
on
a
MUL
TIBUS I
system bus.
8.5.3.3
HANDLING
MORE
THAN
64
INTERRUPTS
If
an 80386 system requires more than 64 interrupt request lines, a third
level
of 8259As in
polled mode can be added to the configuration described
above.
When a third-level control-
ler receives an interrupt request, it drives one of the interrupt request inputs to a slave
controller active. The slave controller sends an interrupt request to the master controller,
and the master controller interrupts the
80386. The slave controller then returns a service-
routine vector to the
80386. The service routine must include commands
to
poll the third
level of interrupt controllers to determine the source of the interrupt request.
The only additional hardware required to handle more than
64
interrupts are the extra 8259As
and the chip-select logic. For maximum performance, third-level interrupt controllers should
be used only for noncritical, infrequently used interrupts.
8.6
80286-COMPATIBLE
BUS
CYCLES
Some devices (the 82258, for example) require an 80286-compatible interface in order to
communicate with the
80386. An 80286-compatible interface must generate the following
signals:
• Address bits
Al
and
AO,
and Byte High Enable (BHE#) from the 80386 BE3#-BEO#
outputs
•
Bus
cycle definition signals
SO#
and
SI#
from the 80386
MjIO#,
W jR#, and
DjC#
outputs
8-17
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