1/0
INTERFACING
8.5.3.1
SINGLE INTERRUPT CONTROLLER
Figure 8-7 shows the connections from the basic
I/O
interface used for the 80386 and a
single 8259A. Programmable Interrupt Controller (PIC#)
is
a chip-select signal from the
address decoding logic.
INT
A#, RD#, and WR# are generated by the bus control logic.
BD7-BDO are connected to the lower eight outputs of the data transceiver. The A2 bit,
connected
to
the 8259A
AO
input,
is
used by the 80386 to distinguish between the two inter-
rupt acknowledge cycles; 8259A register addresses must therefore be located
at
two consec-
utive doubleword boundaries.
When an interrupt occurs, the 8259A activates its Interrupt
(INT)
output, which
is
connected
to the Interrupt Request
(INTR)
input of the 80386. The 80386 automatically executes two
back-to-back interrupt-acknowledge cycles, as described
in
Chapter
3.
The 8259A timing
requirements are as follows:
• Each interrupt-acknowledge cycle must be extended by
at
least one wait state. Wait-state
generator logic must provide for this extension.
• Four idle bus cycles must be inserted between the two interrupt-acknowledge cycles. The
80386 automatically inserts these idle cycles.
8.5.3.2
CASCADED INTERRUPT CONTROLLERS
Several 8259As can be cascaded to handle up to 64 interrupt requests. In a cascaded config-
uration, one 8259A
is
designated as the master controller;
it
receives input from the other
-4-
~
INTE
~~~~
RRUPTING
-#-
DEVICES
-#-
A2
(FROM ADDRESS
LATCH)
PIC#
(CHIP SELECT
FROM
ADDRESS DECODER
FROM
{IOWCH
8US
IORCH
CONTROL INTAH
~
-¥.-
~
27
N/C 12
N/C 13
N/C1S
1
2
3
26
IRO
IRl
·IR2
IR3
IR4
IRS
IR6,
IR7
AO
CASO
CASl
CAS2
Cs
WR
iiii
INTA
8259A
DO
11
Dl
10
D2
9
D3
8
D4
7
DS
6
D6
5
D7
4
-
16
SPEN
INT
17
V
Figure 8-7. Single 8259A Interface
8-16
I
TO
DATA
TRANSCEIVERS
TO
80386
INTRINPUT
G30107
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