Intel 80386

I/O INTERFACING
The 8274 requires a minimum recovery time between back-to-back accesses that is provided
for in the basic
I/0 interface hardware.
8.5.2 82380 Programmable Interrupt Controller
The 82380 Programmable Interrupt Controller (PIC) can be used in interrupt-driven micro-
computer systems.
It has 15 external and 5 internal interrupt requests. Each of the external
requests can be cascaded with an additional 82C59A Interrupt Controller to accommodate
up to 120 external interrupt sources.
The 82380
PIC handles interrupt priority resolution and returns a preprogrammed service
routine vector to the 80386 during an interrupt acknowledge cycle.
It consists of three
82C59A compatible banks. The 82380 Data
Sheet contains detailed information on the 82380
PIC.
When an interrupt occurs, the 82380 PIC activates its Interrupt (INT) output, which is
connected to the Interrupt Request (INTR) input of the 80386. the 80386 automatically
executes two back-to-back interrupt acknowledge cycles, as described in Chapter
3. The
82380
PIC will automatically terminate the interrupt acknowledge cycles by driving its
READYO# signal. Each acknowledge cycle will be extended by five wait states. Also, four
idle states are inserted by the 80386 between two consecutive interrupt acknowledge cycles.
8.5.2.1 CASCADED INTERRUPT CONTROLLERS TO THE 82380 PIC
Each of the external requests of the 82380 PIC can be cascaded with one 'slave' 82C59A
Interrupt Controller. With all its external requests cascaded, the 82380
PIC can handle up
to 120 external requests.
For a cascaded interrupt request, the 82380
PIC will output an 8-bit cascade address on the
data bus during the first interrupt acknowledge cycle. A simple circuit can latch the 8-bit
address and encode it to drive the
CAS signals (CAS2# - CASO#) of the slave controllers.
During the second interrupt acknowledge cycle, the 82380 will not drive the data bus; instead,
the selected slave controller will put the interrupt vector on the data bus for the 80386.
Chapter 9 describes the interface to slave controllers that reside
on a MUL TIBUS I
system bus.
8.5.3 8259A Interrupt Controller
The 8259A Programmable Interrupt Controller is designed for use in interrupt-driven
microcomputer systems. A single 8259A can process up to eight interrupts. Multiple 8259As
can be cascaded to accommodate up to
64 interrupts. A technique to handle more than
64 interrupts
is discussed at the end of this section.
The 8259A handles interrupt priority resolution and returns a preprogrammed service routine
vector to the 80386 during an interrupt-acknowledge cycle. Intel
Application Note AP-59
contains detailed information on configurations of the 8259A.
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