1/0
INTERFACING
• Address Latch Enable (ALE#), Device Enable (DEN), and
Data·
Transmit/Receive
(DT
/R#)
signals
•
I/O
Read Command (IORC#) and
I/O
Write Command (IOWC#) signals for
I/O
cycles
• Memory Read Command (MRDC#) and Memory Write Command (MWTC#) signals
for memory cycles
• Interrupt Acknowledge (INTA#) signal for interrupt-acknowledge cycles
In the following example, the interface
is
constructed using the 80286-compatible bus
controller (82288) and bus arbiter (82289). The 82289, along with the bus arbiters of other
processing subsystems, coordinates control
of
the bus between the 80386 and other bus
masters. The 82288 provides the control signals to perform bus cycles. Communication
between the
80386 and these devices
is
accomplished through PALs that are programmed
to perform all necessary signal translation and generation. Latching and buffering of the
data and address buses
is
performed
by
TTL logic.
Figure 8-8
shows
a block diagram of the interface, which consists of the following parts:
• AO/
Al
generator-Generates
the lower address bits from 80386 BEO#-BE3# outputs
• Address decoder-Determines the device the 80386 will access
• Address
latches-Connect
directly to 80386 address pins A19-A2 and the outputs of the
AO/Al generator
• Data transceivers-Connect directly to 80386 data pins DI5-DO
• SO#/SI#
generator-Translates
80386 outputs into the
SO#
and
SI#
signals
• Wait-state
generator-Controls
the length of the 80386 bus cycle through the READY #
~~
.
• 82288 Bus Controller-Generates the bus command signals
• 82289 Bus
Arbiter-Arbitrates
contention for bus control between the 80386 and other
bus masters
8.6.1
AO/
A 1 Generator
The
AO,
AI,
and BHE# signals are 80286-compatible. These signals are generated from the
80386 byte enables (BEO#-BE3#)
as
shown in Table 8-3. The truth table can be imple-
mented with the logic shown in Figure 8-9.
8.6.2
50#/51#
Generator
SO#
and
SI#
are 80286-compatible status signals that must be provided for the 82288 and
82289. The
SO#/SI# logic in Figure 8-10 generates these signals from 80386 status outputs
(D/C#,
M/IO#,
and W
/R#)
and wait-state generator outputs.
WSI
and WS2 are wait-
state generator outputs that correspond to the first and second wait states of the
80386 bus
cycle. These signals ensure
that
SO#
and S 1 # are valid for two CLK cycles.
8-18
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