Intel 80386

LOCAL BUS INTERFACE
3.3 CLOCK GENERATION
3.3.1 82384 Clock Generator
The 82384 Clock Generator
is a multifunction component of the 80386 system that provides
clocking for synchronous operation of the
80386 and its support components as follows:
• Both CLK2 (a double-frequency clock for the 80386 and some support devices) and CLK
(a system clock for some 80386 support devices) are generated. The phase of the 82384
CLK matches that of the CLK signal generated internally by the 80386.
• The RESET signal for the 80386 and other system components is generated. The RES#
input of the 82384 accepts an asynchronous input from a simple RC circuit or similar
source, synchronizes the signal with CLK, and outputs the active-high
RESET signal to
the
80386 and other system components. The timing and function of the RESET signal
with respect to the
80386 is discussed later in this chapter.
• The 82384 uses the ADS# output of the 80386 (which guarantees setup and hold time to
CLK2) to generate an
ADSO# signal, which is functionally equivalent to ADS# but
guarantees setup and hold times with respect to CLK. Devices that are clocked with the
CLK output of the 82384 can use
ADSO#.
Figure 3-15 shows a typical circuit to connect the 82384 to the 80386.
Either an external frequency source or a third overtone crystal can be used to drive the
82384. The F
jC# input indicates the signal source; if F jC# is pulled high, the 82384 recog-
nizes the signal on its External Frequency Input (EFI) pin as its frequency source. If F jC#
is tied low, the crystal connected to the Xl and X2 pins of the 82384 is its frequency source.
In either case, the source frequency must equal the desired CLK2 frequency. For example,
a
32 MHz crystal yields a 32 MHz CLK2 signal and a 16 MHz 80386 internal clock rate.
3.3.2
Clock Timing
The CLK2 and CLK outputs of the 82384 are both MOS-level outputs with output high
voltage levels of V
cc-0.6V and adequate drive for TTL inputs. CLK2 is twice the frequency
ofCLK.
The internal CLK signal of the 80386 is matched to the CLK output of the 82384 by the
falling edge of the
RESET signal. This operation is described with the RESET function in
Section 3.8.
The skew between the 82384 CLK2 and CLK signals
is maintained at 0-16 nanoseconds
(regardless of clock frequency). For closely timed interfaces, peripheral devices must be
timed by CLK2. Devices that cannot be operated at the
double~clock frequency must use
the CLK output of the 82384. The
80386 interface to these devices must allow for the CLK2-
to-CLK skew.
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