Intel 80386

MEMORY INTERFACING
6.3 DYNAMIC RAM (DRAM) INTERFACE
This section presents a dynamic RAM (DRAM) memory subsystem design that is both cost-
effective and fast. The design can be adapted for a wide variety of speed and system require-
ments to provide high throughput at minimum cost. The DRAM design
in this section is to
illustrate concepts only; the actual circuit has not been tested.
6.3.1 Interleaved Memory
DRAMs provide relatively fast access times at a
low cost per bit; therefore, large memory
systems can be created at
low cost. However, DRAMs have the disadvantage that they require
a brief idle time between accesses to precharge; if this idle time
is not provided, the data in
the DRAM can be lost.
If back-to-back accesses to the same bank of DRAM chips are
performed, the second access must
be delayed by the precharge time. To avoid this delay,
memory should be arranged
so that each subsequent memory access is most likely to be
directed to a different bank. In this configuration, wait time between accesses
is not required
because while one bank of DRAMs performs the current access, another bank precharges
and will be ready to perform the next access immediately.
Most programs tend to make subsequent accesses to adjacent memory locations during code
fetches, stack operations, and array accesses, for example.
If DRAMs are interleaved (i.e.,
arranged
in multiple banks so that adjacent addresses are in different banks), the DRAM
precharge time can be avoided for most accesses. With two banks of DRAMs, one for even
32-bit doubleword addresses and one for odd doubleword addresses, all sequential 32-bit
accesses can be completed without waiting for the DRAMs to precharge.
Even
if random accesses are made, two DRAM banks allow 50 percent of back-to-back
accesses to be made without waiting for the DRAMs to precharge. The precharge time
is
also avoided when the 80386 has no bus accesses to be performed. During these idle bus
cycles, the most recently accessed DRAM bank can precharge
so that the next memory
access to either bank can begin immediately.
The
DRAM memory system design described here uses two interleaved banks of DRAMs.
The
DRAM controller keeps track of the most recently accessed bank in order to guarantee
the precharge time for both banks while allowing memory accesses to begin
as soon as
possible.
6.3.2 DRAM Memory Performance
Table 6-2 shows the performance that can
be obtained using this DRAM design with a
variety of processor and
DRAM speeds. Performance is indicated by the number of wait
states per bus cycle (the number of CLK cycles in addition to the two-CLK minimum time
required to complete the access).
The performance for each processor and
DRAM speed combination is given for both the
case of an access to the opposite bank of interleaved memories, in which
no precharge time
is required, and the case of an access to the same bank, in which the precharge time is
factored in.
6-15