SYSTEM OVERVIEW
The 80386 has separate 32-bit
data
and address paths. A 32-bit memory access can be
completed in only two clock cycles, enabling the bus to sustain a throughput
of
40 megabytes
per second
(at
20 MHz).
By
making prompt transfers between the microprocessor, memory,
and peripherals, the high-speed bus design ensures that the entire system benefits from the
processor's increased performance.
Pipelined architecture enables the
80386 to perform instruction fetching, decoding, execu-
tion, and memory management functions
in
parallel. The
six
independent units
that
make-
up the
80386 pipeline are described in detail
in
Chapter
2.
Because the 80386 prefetches
instructions and queues them internally, instruction fetch and decode times are absorbed
in
the pipeline; the processor rarely has to wait for an instruction to execute.
Pipelining
is
not unusual in modern microprocessor architecture; however, including the
memory management unit
(MMU)
in the on-chip pipeline
is
a unique feature of the 80386.
By
performing memory management on-chip, the 80386 eliminates the serious access delays
typical
of
implementations
that
use off-chip memory management units. The benefit
is
not
only high performance but also relaxed memory-access time requirements, hence lower system
cost.
The
integrated memory management and protection mechanism translates logical addresses
to physical addresses and enforces the protection rules necessary for maintaining task integ-
rity in a multitasking environment. The paging function simplifies the operating-system
swapping algorithms by providing a uniform mechanism for managing the physical structure
of
memory.
Task switching occurs frequently in real-time multitasking or multiuser systems. To perform
task switching efficiently, the
80386 incorporates special high-speed hardware. Only a single
instruction or an interrupt
is
needed for the 80386 to perform a complete task switch. A
20-MHz 80386 can save the state of one task (all registers), load the state of another task
(all registers, even segment and paging registers if required), and resume execution in less
than
14
microseconds
(at
20 MHz). For less sophisticated task and interrupt handling, the
latency can be as short
as
2.9 microseconds
(at
20 MHz).
1.2
COPROCESSORS
The
performance of most applications can be enhanced
by
the use of specialized coproces-
sors. A coprocessor provides the hardware to perform functions that would otherwise be
performed in software. Coprocessors extend the instruction set of the
80386.
The
80386 has a numeric coprocessor interface that can support one of
two
coprocessors:
the
80387 or the 80287. For applications that benefit from high-precision integer and
floating-point calculations, these numeric coprocessors provide full support for the
IEEE
standard for floating-point operations. Both the 80387 and 80287 are software compatible
with the
8087, an earlier numeric coprocessor.
At
16
MHz, the 80387 operates about eight
times faster than a 5-MHz
80287. However, the 80287
is
fast enough for many applications
and
is
a cost-effective solution for many designs. The 80386 therefore offers the system
designer the choice of low-cost or high-performance numeric solutions.
1-3
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