Intel 80386

LOCAL BUS INTERFACE
o All address bus outputs are driven low. For a halt condition, BE2# is active; for a shutdown
condition,
BEO# is active. These signals are used by external devices to respond to the
halt or shutdown cycle.
READY # must be asserted to complete the halt or shutdown cycle. The 80386 will remain
in the halt or shutdown condition until...
Q NMI goes high; 80386 services the interrupt
• RESET goes high; 80386 is reinitialized
In the halt condition (but not
in the shutdown condition), if maskable interrupts are enabled,
an active
INTR input will cause the 80386 to end the halt cycle to service the interrupt. The
80386 can service processor extension
(PEREQ input) requests and HOLD (HOLD input)
requests while in the halt or shutdown condition.
3.1.9 B516 Cycle
The 80386 can perform data transfers for both 32-bit and 16-bit data buses. A control input,
BS 16#, allows the bus size to be specified for each bus cycle. This dynamic bus sizing gives
the 80386 flexibility in using 16-bit components and buses.
The BSI6# input causes the 80386 to perform data transfers for a 16-bit data bus (using
data bus signals DI5-DO) rather than a 32-bit data bus. The 80386 automatically performs
two or three cycles for
data transfers larger than 16 bits and for misaligned (odd-addressed)
16-bit transfers.
BSI6# must be supplied by external hardware, either through chip select decoding or directly
from the addressed device.
BSI6# is sampled at the start of Phase 2 only in CLK cycle as
long
as ADS# is not active. If BS 16# and READY # are sampled low in the same CLK cycle,
the 80386 assumes a 16-bit data bus.
The BSI6# control input affects the performance of a data transfer only for data transfers
in which 1)
BEO# or BEl# is active and 2) BE2# or BE3# is active at the same time. In
these transfers, the 80386 must perform two bus cycles using only the lower half of the
data
bus.
If a BS16 cycle requires an additional bus cycle, the 80386 will retain the current address
for the second cycle. Address pipelining cannot be used with
BS 16 cycles because address
pipelining requires that the next address be generated
on the bus before the end of the current
bus cycle. Therefore, because both signals are sampled
at the same sampling window, BS16#
must be active before or
at the same time as NA# to guarantee 16-bit operation. Once NA#
is sampled active in a bus cycle and BS 16# is not active at that time, BS 16# must be negated
for the remainder of the bus cycle.
If BS16# is asserted during the last clock of the bus cycle and NA# was not asserted previ-
ously in the bus cycle, then the processor performs a 16-bit bus cycle. This
is true, even if
NA# is asserted during the last clock of the bus cycle. Figure 3-12 illustrates this logic.
3-19