Intel 80386

LOCAL BUS INTERFACE
A 74FI09 flip-flop divides CLK2 by two to generate CLK. CLK has the same phase as the
80386 internal clock, going low during phase 1 and high during phase 2. A 74F379 generates
a synchronous RESET output, ensuring that the falling edge of RESET occurs during
phase 2.
The recommended circuit does not implement the ADS# synchronization feature of the 82384.
The ADS# synchronizer is not necessary if all registered PALs in the local bus controller
use CLK2. Clocking PALs with CLK2 (rather than CLK) is the preferred method since it
minimizes skew between the processor and its surrounding logic. If it is necessary to have
an address status signal synchronous to CLK, then an ADS# synchronizer may be built
using a delay line and flip-flop, as shown in Figure 3-18.
An alternative method of generating CLK2 is to use a TTL oscillator coupled to a 74ACT244
buffer. Although a typical 74ACT244 datasheet does not guarantee an output compatible
with the 80386 CLK2 input, some manufacturers devices have been observed to have suffi-
ciently fast rise/fall times (4 ns at CL=80 pf), as well as the necessary swing, to meet the
80386 CLK2 requirements. This approach is recommended if the 80386 must run synchron-
ously with an external clock (i.e. EFI). Similarly, if a CMOS level swing is required on
CLK, a 74ACI09 flip-flop may be used instead of the 74F109.
3.4 INTERRUPTS
Both hardware-generated and software-generated interrupts can alter the programmed
execution of the 80386. A hardware-generated interrupt occurs in response to an active input
on one of two 80386 interrupt request inputs (NMI or INTR). A software-generated inter-
rupt occurs in response to an INT instruction or an exception (a software condition that
elK
10NS
G30107
Figure 3-18. ADS# Synchronizer
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