Intel 80386

inter
LOCAL BUS INTERFACE
requires servicing). For complete information on software-generated interrupts, see the 80386
Programmer's Reference Manual.
In response to an interrupt request, the
80386 processes the interrupt (saves the processor
state on the stack, plus task information if a task switch
is required) and services the inter-
rupt (transfers program execution to one of 256 possible interrupt service routines). Entry-
point descriptors to service routines or interrupt tasks are stored in a table (Interrupt
Descriptor Table or
IDT) in memory. To access a particular service routine, the 80386 must
obtain a vector, or index, to the table location
that contains the corresponding descriptor.
The source of this vector depends
on the type of interrupt; if the interrupt is maskable (INTR
input active), the vector is supplied by the 8259A Interrupt Controller. If the interrupt is
nonmaskable (NMI input active), location 2 in the IDT is used automatically.
The
NMI request and the INTR request differ in that the 80386 can be programmed to
ignore
INTR requests (by clearing the interrupt flag of the 80386). An NMI request always
provokes a response from the
80386 unless the 80386 is already servicing a previous NMI
request. In addition, an INTR request causes the 80386 to perform two interrupt-
acknowledge bus cycles to fetch the service-routine vector. These bus cycles are not required
for an
NMI request, because the vector location for an NMI request is fixed.
Under the following two conditions a service routine will not be interrupted by an incoming
interrupt:
• The incoming interrupt is an INTR request, and the 80386 is programmed to ignore
maskable interrupts. (The
80386 is automatically programmed to ignore maskable inter-
rupts when it receives any interrupt request. This condition may be changed
by the inter-
rupt service routine.) In this case, the
INTR request will be serviced only if it is still
active when maskable interrupts are reenabled.
o The incoming interrupt is an NMI, and the 80386 is servicing a previous NMI. In this
case, the
NMI is saved automatically to be processed after the IRET instruction in the
NMI service routine has been executed. Only one NMI can be saved; any others that
occur while the 80386 is servicing a previous NMI will not be recognized.
If neither of the above conditions is true, and an interrupt occurs while the 80386 is servicing
a previous interrupt, the new interrupt
is processed and serviced immediately. The 80386
then continues with the previous service routine. The last interrupt processed is the first one
serviced.
If an NMI request and an INTR request arrive at the 80386 simultaneously, the NMI
request is processed first. Multiple hardware interrupts arriving at the 8259A are processed
according to their priority and are sent to the
80386 INTR input one at a time.
3.4.1
Non-Maskable Interrupt (NMI)
The NMI input of the 80386 generally signals a catastrophic event, such as an imminent
power loss, a memory error, or a bus parity error. This input
is edge-triggered (on a low-to-
high transition) and asynchronous. A valid signal
is low for eight CLK2 periods before the
transition and high eight CLK2 periods after the transition. The
NMI signal can be
asynchronous to CLK2.
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