Intel 80386

LOCAL BUS INTERFACE
An NMI request automatically causes the 80386 to execute the service routine correspond-
ing to location 2 in the IDT. The 80386 will not service subsequent NMI requests until the
current request has been serviced. The 80386 disables INTR requests (although these can
be reenabled in the service routine) in Real Mode. In Protected Mode, the disabling of
INTR requests depends on the gate in IDT location 2.
3.4.2 Maskable Interrupt (lNTR)
The INTR input of the 80386 allows external devices to interrupt 80386 program execution.
To ensure recognition by the 80386, the INTR input must be held high until the 80386
acknowledges the interrupt by performing the interrupt acknowledge sequence. The INTR
input is sampled at the beginning of every instruction; it must be high at least eight CLK2
periods prior to the instruction to guarantee recognition as a valid interrupt. This require-
ment reduces the possibility of false inputs from voltage glitches. In addition, maskable
interrupts must enabled in software for interrupt recognition. The INTR input may be
asynchronous to CLK2.
The INTR signal is usually supplied by the 8259A Programmable Interrupt Controller, which
in turn is connected to devices that require interrupt servicing. The 8259A, which is controlled
by commands from the 80386 (the 8259A appears as a set of I/O ports), accepts interrupt
requests from devices connected to the 8259A, determines the priority for transmitting the
requests to the 80386, activates the INTR input, and supplies the appropriate service routine
vector when requested.
An INTR request causes the 80386 to execute two back-to-back interrupt acknowledge bus
cycles, as described earlier in Section 3.1.4.
3.4.3 Interrupt Latency
The time that elapses before an interrupt request is serviced (interrupt latency) varies
according to several factors. This delay must be taken into account by the interrupt source.
Any of the following factors can affect interrupt latency:
• If interrupts are masked, an INTR request will not be recognized until interrupts are
reenabled.
• If an NMI is currently being serviced, an incoming NMI request will not be recognized
until the 80386 encounters the IRET instruction.
• If the 80386 is currently executing an instruction, the instruction must be completed. An
interrupt request is recognized only on an instruction boundary. (However, Repeat String
instructions can be interrupted after each iteration.)
• Saving the Flags register and CS:EIP registers (which contain the return address) requires
time.
• If interrupt servicing requires a task switch, time must be allowed for saving and restoring
registers.
• If the interrupt service routine saves registers that are not automatically saved by the
80386, these instructions also delay the beginning of interrupt servicing. .
3-31