Intel 80386

LOCAL BUS INTERFACE
The longest latency occurs when the interrupt request arrives while the 80386 is executing
a long instruction such as multiplication, division, or a task-switch in the Protected mode.
If the instruction loads the Stack Segment register, an interrupt is not processed until after
the following instruction, which should be an ESP load. This allows the entire stack pointer
to be loaded without interruption.
If an instruction sets the interrupt flag (thereby enabling interrupts), an interrupt is not
processed until after the next instruction.
3.5 BUS LOCK
In a system in which more than one device may control the local bus, locked cycles must be
used when it is critical that two or more bus cycles follow one another immediately. Other-
wise, the cycles can be separated by a cycle from another bus master.
Any bus cycles that must be performed back-to-back without any intervening bus cycles by
other bus masters should be locked. The use of a semaphore is one example of this precept.
The value of a semaphore indicates a condition, such as the availability of a device. If the
80386 reads a semaphore to determine that a device is available, then writes a new value to
the semaphore to indicate that it intends to take control of the device, the read cycle and
write cycle should be locked to prevent another bus master from reading from or writing to
the semaphore in between the two cycles. The erroneous condition that could result frpm
unlocked cycles is illustrated in Figure 3-19. .
The LOCK# output of the 80386 signals the other bus masters that they may not gain
control of the bus. In addition, an 80386 with LOCK# asserted will not recognize a HOLD
request from another bus master.
3.5.1 Locked Cycle Activators
The LOCK# signal is activated explicitly by the LOCK prefix on certain instructions. LOCK#
is also asserted automatically for an XCHG instruction, a descriptor update, interrupt
acknowledge cycles, and a page table update.
3.5.2 Locked Cycle Timing
LOCK# is activated on the CLK2 edge that begins the first locked bus cycle. LOCK# is
deactivated when READY # is sampled low at the end of the last bus cycle to be locked.
LOCK# is activated and deactivated on these CLK2 edges whether or not address pipelining
is used. If address pipe lining is used, LOCK# will remain active until after the address bus
and bus cycle status signals have been asserted for the pipelined cycle. Consequently, the
LOCK# signal can extend into the next memory aCCeSS cycle that does not need to be locked.
(See Figure 3-20.) The result is that the use of the bus by another bus master is delayed by
one bus cycle.
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