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Intel 80386

Intel 80386
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LOCAL BUS INTERFACE
BUS MASTER 1
READS
VALUE 0 = NOT BUSY
BUS
MASTER 1
WRITES
VALUE 1 = BUSY
BUS
MASTER
HAS CONTROL
OF
DEVICE
SEMAPHORE
-0)
--0
NO ERROR
SEMAPHORE
BUS
MASTER 1 G
READS - 0
VALUE 0 =
NOT
BUSY
/
/
LOCKED
CYCLES
BUS
MASTER 2
READS
VALUE 1 = BUSY
BUS MASTER 2
WAITS FOR
VALUE TO
CHANGE
UNLOCKED /
~
~
CYCLES \
L..:J
BUS MASTER 2
READS
VALUE
O=NOT
BUSY
,
BUS MASTER 1 \
WRITES
--
r;-l
VALUE 1 = BUSY
L..J
[2]-
BUS MASTER 2
WRITES
VALUE 1 = BUSY
ERROR
BOTH BUS MASTERS
TRY
TO
CONTROL DEVICE
Figure
3-19.
Error
Condition
Caused
by
Unlocked
Cycles
3.5.3 LOCK# Signal Duration
G30107
The maximum duration of the LOCK# signal affects the maximum HOLD request latency
because HOLD
is
not recognized until LOCK# goes inactive. The duration of LOCK#
depends
on
the instruction being executed and the number of wait states per cycle.
The longest duration of LOCK#
in
real mode
is
two bus cycles plus approximately two
clocks. This occurs during the
XCHG
instruction and
in
LOCKed read-modify-write opera-
tions. The longest duration of LOCK#
in
protected mode
is
five
bus cycles plus approxi-
mately fifteen clocks. This occurs when an interrupt (hardware or software interrupt)_
O~Cl!.rS
3-33

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