COPROCESSOR HARDWARE INTERFACE
5.1.3
80287
Clock Input
The 80287 can operate from the CLK or CLK2 output of the 82384 or a dedicated clock
oscillator. To operate the 80287 from CLK or CLK2, the Clock Mode (CKM) pin of the
80287 must be tied to ground.
In
this configuration, the 80287 divides the system clock
frequency internally by three.
The CKM pin of the 80287
is
tied high to operate the 80287 from a dedicated MOS-level
clock.
In
this configuration, the 80287 does not internally divide the clock frequency; it
operates directly from the external clock. An 8284A clock driver and an appropriate crystal
can be used to provide the 80287 with the desired clock frequency.
5.2
80387
NUMERIC COPROCESSOR INTERFACE
The 80387 achieves significant enhancements
in
performance and instruction capabilities
over the 80287.
It
runs
at
internal clock rates of
16
or
20
MHz. To achieve maximum speed,
the interface with the 80386
is
synchronous and includes a full 32-bit data bus. Detailed
information
on
other 80387 enhancements can be found
in
the 80387 Data Sheet.
The 80387
is
designed to run either fully synchronously or pseudosynchronously with the
80386.
In
the pseudosynchronous mode, the interface logic of the 80387 runs with the clock
signal of the 80386, whereas internal logic runs with a different clock signal.
5.2.1
80387
Connections
The connections between the 80386 and the 80387 are shown
in
Figure
5-2
and are described
as
follows:
• The 80387 BUSY
#,
ERROR#, and PEREQ outputs are connected to corresponding 80386
inputs.
• The 80387
RESETIN
input
is
connected to the 82384 RESET output.
• The 80387 Numeric Processor Select chip-select inputs (NPS1# and NPS2) are connected
directly to the 80386
MjIO#
and
A3l
outputs, respectively. For coprocessor cycles,
MjIO#
is
always
low;
A3l,
high.
• The 80387 Command (CMDO#) input differentiates data from commands. This input
is
connected directly to the 80386
A2
output. The 80386 outputs address 800000F8H when
writing a command or reading status, address 800000FCH when writing or reading data.
• All
32
bits (D3l-DO) of the 80386 data bus connect directly to the data bus of the 80387.
Because the data lines are connected directly, any local data bus transceivers must be
disabled when the 80386 reads data from the 80387.
• The 80387 READY
#,
ADS#, and W jR# inputs are connected to the corresponding pins
on
the 80386. READY # and ADS# are used by the 80387 to track bus activity and
determine when W jR#, NPS1#, NPS2, and Status Enable
(STEN)
can be sampled.
5-4
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