1/0
INTERFACING
Interrupt-acknowledge cycles generate the Interrupt Acknowledge
(INTA#)
output, which
is
returned to the 8259A Interrupt Controller.
The bus controller also controls the
READY
# input to the 80386
that
ends each bus cycle.
The
PAL-2 bus control
PAL
counts wait states and returns
READY
# after
the
number
of
wait states required by the accessed device.
The
design of this portion of the bus controller
depends on the requirements
of
the system; relatively simple systems need less wait-state
logic
than
more complex systems. The basic interface described here uses a
PAL
device to
generate
READY
#;
other designs may use counters
and/or
shift registers.
If
several
I/O
devices reside on the local bus,
READY
# logic can be simplified by combin-
ing into a single input the chip selects for devices
that
require the same number of wait
states.
The
CSIO#
input of
PAL-l
generates the same number of wait states for all
I/O
accesses. Adding wait states to some devices to make the wait-state requirements
of
several
devices the same does not significantly impact performance.
If
the response
of
the device
is
already slow (four wait states, for example), the additional wait state amounts to a relatively
small delay. Typically,
I/O
devices are used infrequently enough
that
the access time
is
not
critical.
8.4
TIMING ANALYSIS FOR
1/0
OPERATIONS
In this section, timing requirements for devices
that
use the basic
I/O
interface are discussed.
The values
of
the various device specifications are examples only; for correct timing analysis,
always refer to the latest
data
sheet for the particular device.
Timing for 80386
I/O
cycles
is
identical to memory cycle timing
in
most respects;
in
partic-
ular, timing depends on the design of the interface. The worst-case timing values are calcu-
lated by assuming the maximum delay
in
the address latches, chip select logic, and command
signals, and the longest propagation delay through the
data
transceivers
(if
used). These
calculations yield the minimum possible access time for an
I/O
access for comparison with
the access time of a particular
I/O
device.
Wait
states must be added to the basic worst-
case values until read and write cycle times exceed minimum device access times.
The timing requirement for the address decoder dictates
that
the logic be combinational (not
latched or registered) with a propagation delay less
than
the maximum delay calculated
below.
The
CSIWS
signal requires a maximum decoder delay
of
38.75 nanoseconds:
(3
x
CLK2
period)
(3 x 31.25)
- 80386
Addr
Valid
-
38
= 40.75 nanoseconds
(CLK2
= 32
MHz)
8-9
-
PAL
setup
-
15
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