Intel 80386

I/O INTERFACING
The CSOWS signal must be slightly faster in order to activate NA#:
(3 x CLK2 period) - 80386 Addr Valid - (2 x OR prop. delay)
- 80386 NA# setup
(3 x 31.25) -38 -(2x6)
- 10
= 33.75 nanoseconds
(CLK2
= 32 MHz)
The timings of the other signals can be calculated from the waveforms in Figure 8-5. In the
following example, the timings for
I/O accesses are calculated for CLK2 = 32 MHz and
B-series
PALs. All times are in nanoseconds.
tAR: Address stable before Read (IORC# fall)
tA
W: Address stable before Write (IOWC# fall)
(5 x CLK2 period) - PAL RegOut Max - Latch Enable Max
+
PAL RegOut Min
(5 x 31.25)
-12 -11.5
+ 0
= 132.75 nanoseconds
tRR: Read
(IORC#) pulse width
(9 x CLK2 period)
- PAL RegOut Max + PAL RegOut Min
(9 x 31.25)
-12 +0
= 269.25 nanoseconds
tWW: Write
(IOWC#) pulse width
(10 x CLK2 period)
- PAL RegOut Max + PAL RegOut Min
(10 x 31.25)
- 12 + 0
= 300.5 nanoseconds
tRA: Address hold after Read
(IORC# rise)
(6 x CLK2 period)
- PAL RegOut Max + PAL RegOut Min
+ Latch Enable Min
(6 x 31.25)
- 12 + 0
+ 5
= 180.5 nanoseconds
8-10