1/0
INTERFACING
8.3.3
Data Transceiver
Standard 8-bit transceivers (74x245, in this example) provide isolation and additional drive
capability for the 80386 data bus. Transceivers are necessary to prevent the contention
on
the data bus
that
occurs if some devices are slow to remove read data from the data bus
after a read cycle.
If
a write cycle follows a read cycle, the 80386 may drive the data bus
before a slow device has removed its outputs from the bus, potentially causing bus contention
problems. Transceivers can be omitted only if the data float time of the device
is
short enough
and the load on the 80386 data pins meets device specifications.
A bus interface must include enough transceivers to accommodate the device with the most
inputs and outputs on the data bus.
If
the widest device has
16
data bits and if the
I/O
addresses are located
so
that
all devices are connected only to the lower half of the data bus,
only two 8-bit transceivers are needed.
The 74x245 transceiver
is
controlled through two input signals:
• Data Transmit/Receive (DT
/R#)-When
high, this input enables the transceiver for a
write cycle. When
low,
it enables the transceiver for a read cycle. This signal
is
just a
latched version of the 80386 W
/R#
output.
• Data Enable
(DEN#)-When
low,
this input enables the transceiver outputs. This signal
is
generated by the bus control logic.
Note
that
in a system using the 82380, the data transceivers must be disabled whenever the
80386 performs a read access to one of the internal registers of the 82380. Otherwise, both
the 82380 and the data transceivers will be driving the local bus which causes
data
conten-
tion. This can be avoided by decoding the 82380 address space in the bus controller logic.
Together with the bus cycle definition signals
(W
/R#,
M/IO#),
the data transceivers can
be disabled by deactivating the
DEN#
signal.
8.3.4
Bus
Control Logic
The bus control logic for the basic
I/O
interface
is
the same
as
the logic for the memory
interface described in Section 6.2. The bus controller decodes the 80386 status outputs
(W
/R#,
M/IO#,
and D
/C#)
and activates a command signal for the type of bus cycle
requested. The command signal corresponds to the bus cycle types (described in Chapter 3)
as
follows:
• Memory data read and memory code read cycles generate the Memory Read Command
(MRDC#)
output.
MRDC#
commands the selected memory device to output data.
•
I/O
read cycles generate the
I/O
Read Command (IORC#) output. IORC# commands
the selected
I/O
device to output data.
• Memory write cycles generate the Memory Write Command (MWTC#) output. MWTC#
commands the selected memory device to receive the data on the data bus.
•
I/O
write cycles generate the
I/O
Write Command (IOWC#) output. IOWC# commands
the selected memory device to receive the data
on
the data bus.
8-8
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