inter
MUL TIBUS® I AND
80386
MUL
TIBUS I protocols are described in detail in the Intel MULTlBUS® I Architecture
Reference Book.
One method of constructing an interface between the 80386 and the
MUL
TIBUS I
is
to
generate all
MUL
TIBUS I signals using only
TTL
and PAL devices. A simpler method
is
to use the 80286-compatible interface described
in
Chapter
8.
The latter option
is
described
in the
MUL
TIBUS I interface example in this chapter.
9.2
MUL TIBUS® I INTERFACE EXAMPLE
The
MULTI
BUS I interface presented
in
the following example consists of the 80286-
compatible 82289 Bus Arbiter and 82288 Bus Controller. The 82289, along with the bus
arbiters of other processing subsystems, coordinates control of the MUL TIBUS
I;
the 82288
provides the control signals to perform
MUL
TIBUS I accesses. Communication between
the 80386 and these devices
is
accomplished through PALs that are programmed to perform
all necessary signal translation and generation. Latching and buffering of the data and address
buses
is
performed by
TTL
logic.
Figure
9-1
shows a block diagram of the interface, which consists of the following parts:
• AO/Al
generator-Generates
the lower address bits from 80386 BEO#-BE3# outputs
• Address
decoder-Determines
whether the bus cycle requires a MUL TIBUS I access
• MULTIBUS I address
latches-Connect
directly to 80386 address pins A23-A2 and the
outputs of the
AO
/ A 1 generator
• MULTI BUS I data latch/transceivers-Connect directly to 80386 data pins DI5-DO
• SO#/SI#
generator-Translates
80386 outputs into the
SO#
and
SI#
signals
• Wait-state
generator-Controls
the length of the 80386 bus cycle through the READY #
signal
• 82288 Bus
Controller~Generates
the
MUL
TIBUS I command signals
o 82289 Bus
Arbiter-Arbitrates
contention for bus control between the 80386 and other
MUL
TIBUS I masters
These elements
of
the 80286-compatible interface are described
in
detail
in
Chapter
8.
The
block diagram in Figure
9-1
does not include the 80386 local bus interface and local resources.
In a complete system, some logic (for example, the address decoder)
is
common to both
MUL
TIBUS I and local bus interfaces. The following discussion includes only the logic
necessary for the
MUL
TIBUS I interface.
9.2.1
Address
Latches and Data Transceivers
MUL
TIBUS I allows up to
24
address lines and
16
data lines. In this example, the
MUL TIBUS addresses are located
in
a 256-kilobyte range between
FOOOOOH
and F3FFFFH,
so
that all
24
address lines are used. The
16
data lines correspond to the lower half of the
80386 data bus.
9-2
To Next Page
Loading...
