CHAPTER
11
PHYSICAL
DES~GN
AND
DEBUGG~NG
This chapter outlines recommendations for providing adequate power to the 80386, address-
ing high-frequency issues
that
do
not exist for lower-frequency systems, achieving the proper
thermal environment for the 80386, and building an 80386-based system successfully. The
guidelines presented here allow the user to gain the full benefits of the high-performance
80386.
11.1
POWER AND GROUND REQUIREMENTS
The
CHMOS
III 80386 differs from previous
HMOS
microprocessors
in
that
its power
dissipation
is
primarily capacitive; there
is
almost
no
DC power dissipation. Power dissipa-
tion depends mostly on frequency.
Power dissipation can be distinguished
as
either internal (logic) power or
I/O
(bus) power.
Internal power varies with operating frequency and to some extent with wait states and
software. Internal power increases with supply voltage also. Process variations in manufac-
turing affect internal power, although to a lesser extent than with
NMOS
processes.
I/O
power, which accounts for roughly one-fifth of the total power dissipation, varies with
frequency and voltage.
It
also depends
on
capacitive bus load. Capacitive bus loadings for
all output pins are specified in the 80386 data sheet. The 80386 output valid delays will
increase if these loadings are exceeded. The addressing pattern of the software can affect
I/O
power by changing the effective frequency at the address pins. The variation
in
frequency
at
the data pins tends to be smaller; thus varying data patterns should not cause a significant
change in power dissipation.
11.1.1 Power and Ground
Planes
Power
and ground planes must be used
in
80386 systems to minimize noise. Power and
ground lines have inherent inductance and capacitance, therefore an impedance
Z
= (L/C)I/2. The total characteristic impedance for the power supply can be reduced by
adding more lines. This effect
is
illustrated in Figure 11-1, which shows that two lines in
parallel have half the impedance of one. To reduce the impedance even further, the user
should add more lines. In the limit, an infinite number of parallel lines, or a plane, results
in the lowest impedance.
Planes also provide the best distribution of power and ground.
The 80386 has 20
Vee
pins and
21
Vss
(ground) pins. All power and ground pins must be
connected to a plane. Ideally, the 80386
is
located
at
the center of the board, to take full
advantage of these planes.
Although the 80386 generally demands less power than the 80286, the possibility for power
surges
is
increased due to higher frequency and pin count. Peak-to-peak noise on
Vee
relative
to
Vss
should be maintained
at
no
more than 400 mV, and preferably
no
more than 200 mV.
11-1
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