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COPROCESSOR HARDWARE INTERFACE
•
ERROR#
is
asserted after a coprocessor math instruction results in an error
that
is
not
masked by the coprocessor's control register. The data sheets for the 80287 and 80387
describe these errors and explain how to mask them under program control.
If
an error
occurs,
ERROR#
goes active before BUSY # goes inactive,
so
that the 80386 can take
care of the error before performing another data transfer.
5.1
80287
NUMERIC
COPROCESSOR
INTERFACE
The 80287
is
described in this section only as
it
relates to the 80386. For a complete functional
description
of
the 80287, see the 80287 Data Sheet.
5.1.1
80287
Connections
The connections between the 80386 and the 80287 are shown
in
Figure
S-1.
These connec-
tions are made as follows:
• The 80287 BUSY
#,
ERROR#, and PEREQ outputs are connected to corresponding 80386
inputs.
• The 80287
RESET
input is connected to the 82384 RESET output.
• The 80287 Numeric Processor Select chip-select inputs
(NPSI#
and NPS2) are connected
to the latched
M/IO#
and
A31
outputs, respectively. For coprocessor cycles,
M/IO#
is
always
low;
A31, high.
• The 80287 Command inputs
(CMDI
and CMDO) differentiate data from commands.
These inputs are connected to ground and the latched A2 output, respectively. The 80386
outputs address 800000F8H when writing a command, address 800000FCH when writing
or reading data.
• The lower half
of
the data bus connects to the
16
data bits of the 80287. The 80386
transfers data to and from the 80287 only over the DIS-DO lines.
• The 80287 Numeric Processor Read (NPRD#) and Numeric Processor Write
(NPWR#)
inputs are connected to
I/O
read and write signals from local bus control logic. The
configuration of this logic depends
on
the overall system.
• The 80287 Processor Extension Acknowledge (PEACK#) input
is
pulled high. In an 80286
system, the 80286 generates PEACK# to disable the PEREQ output of the 80287
so
that
extra data
is
not transferred. Because the 80386 knows the length of the operand and will
not transfer extra data, PEACK#
is
not needed or used
in
80386 systems.
5.1.2
80287
Bus
Cycles
When the 80386 encounters a coprocessor instruction, it automatically generates one or more
I/O
cycles to
I/O
addresses 800000F8H and 800000FCH. The 80386 performs all neces-
sary bus cycles to memory and transfers data to and from the 80287
on
the lower half
of
the
5-2
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