Intel 80386

CHAPTER 5
COPROCESSOR HARDWARE INTERFACE
A numeric coprocessor enhances the performance of an 80386 system by performing numeric
instructions
in parallel with the 80386. The 80386 automatically passes on these instructions
to the coprocessor
as it encounters them.
Intel offers two numeric coprocessors:
• The 80287 performs 16-bit data transfers. With the proper interface, the 80386 supports
the
80287.
•
The 80387 performs 32-bit data transfers and interfaces directly with the 80386. The
80387 supports the instruction set of both the 80287 and the 8087, offering additional
enhancements that include full compatibility with the IEEE Floating-Point Standard, draft
10. The performance of a 16-MHz 80387 is about eight times faster than that of a
5-MHz
80287.
Either an 80287 or an 80387 numeric coprocessor can be included in an 80386 system. The
80386 samples its ERROR# input during initialization to determine which coprocessor is
present. As mentioned above, the 80287 and 80387 require different interfaces and therefore
slightly different protocols. The
80287 data bus is 16 bits wide, whereas the 80387 data bus
is 32 bits wide.
Data transfers to and from a coprocessor are accomplished through I/O addresses
800000F8H and 800000FCH; these addresses are automatically generated by the 80386 for
coprocessor instructions and allow simple chip-select generation using
A31 (high) and
M/IO# (low). Because A31 is high for coprocessor cycles, the coprocessor addresses lie
outside the range of the programmed
I/O address space and are easy to distinguish from
programmed
I/O addresses. Coprocessor usage is independent of the I/O privilege level of
the
80386.
The 80386 has three input signals for controlling data transfer to and from an 80287 or
80387 coprocessor: BUSY#, Coprocessor Request (PEREQ), and ERROR#. These signals,
which are level-sensitive and may be asynchronous to the CLK2 input of the
80386, are
described
as follows:
• BUSY # indicates that the coprocessor is executing an instruction and therefore cannot
accept a
new one. When the 80386 encounters any coprocessor instruction except FNINIT
and FNCLEX, the BUSY # input must be inactive (high) before the coprocessor accepts
the instruction. A new instruction therefore cannot overrun the execution of the current
coprocessor instruction. (Certain
80387 instructions can be transferred when BUSY # is
active (low). These instructions are queued and do not interfere with the current
instruction. )
• PEREQ indicates that the coprocessor needs to transfer data to or from memory. Because
the coprocessor
is never a bus master, all input and output data transfers are performed
by the 80386. PEREQ always goes inactive before BUSY # goes inactive.
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