Intel 80386 - Page 7

PREFACE
• Chapter 6, "Memory Interfacing." This chapter discusses techniques for designing memory
subsystems for the 80386.
• Chapter 7, "Cache Subsystems." This chapter describes cache memory subsystems, which
provide higher performance
at lower relative cost.
• Chapter 8, "I/O Interfacing." This chapter discusses techniques for connecting I/O devices
to
an 80386 system.
• Chapter 9, "MULTIBUS® I and 80386." This chapter describes the interface between
an 80386 system and the Intel
MUL TIBUS I multi-master system bus.
• Chapter 10, "MULTIBUS® II and 80386." This chapter describes the interface between
an 80386 system and the Intel
MULTI BUS II multi-master system bus.
• Chapter 11, "Physical Design and Debugging." This chapter contains recommendations
for constructing and debugging 80386 systems.
• Chapter 12, "Test Capabilities." This chapter describes 80386 test procedures.
• Appendix A contains descriptions of the components of the basic memory interface
described in Chapter
6.
• Appendix B contains descriptions of the components of the 80387 emulator described in
Chapter
5.
• Appendix C contains descriptions of the components of the dynamic RAM subsystem
. described in Chapter 6.
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