Intel 80386 - Page 9

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TABLE OF CONTENTS
Page
3.5.2 Locked Cycle Timing .................................................................................. 3-32
3.5.3
LOCK# Signal Duration ........ ............ .................... ............ .......... ............... 3-32
3.6
HOLDIHLDA (Hold Acknowledge) ......................................... :....................... 3-33
3.6.1 HOLDIHLDA Timing .. , ..... .............. ......................... ............... ................ ..... 3-33
3.6.2 HOLD Signal Latency ................................................................................. 3-35
3.6.3 HOLD State Pin Conditions .............. .......... ........ ...... ............ ................ ...... 3-35
3.7 Reset ............................................................................................................. 3-35
3.7.1 RESET Timing ............................................................................................ 3-35
3.7.2 80386 Internal States ................... '.............................................................. 3-36
3.7.3
80386 External States ............................................................................... 3-38
CHAPTER 4
PERFORMANCE
CONSIDERATIONS
4.1 Wait States and Pipelining ................................ .......... .............. ................ ..... 4-1
CHAPTER 5
COPROCESSOR HARDWARE INTERFACE
5.1 80287 Numeric Coprocessor Interface .......................................................... 5-2
5.1.1 80287 Connections ................ .............. .............. ...... ...... ........ ........ ............ 5-2
5.1.2 80287 Bus Cycles .. .................. ........................................ ................ .......... 5-2
5.1.3
80287 Clock Input ........... .............. ............ .............. .......... ............. ............ 5-4
5.2
80387 Numeric Coprocessor Interface .. ........ ........ ...... ...... ...... ...................... 5-4
5.2.1 80387 Connections . ... ... ....... ....... ............ ..... ............ .............. ........ ....... ..... 5-4
5.2.2 80387 Bus Cycles ...................................................................................... 5-6
5.2.3 80387 Clock Input . ...................... ...... ................ ......... .............. ........ ..... ..... 5-6
5.3
Local Bus Activity with the 80287/80387 ........ .............. .................. .............. 5-6
5.4 Designing an Upgradable 80386 System ...................................................... 5-7
5.4.1 80287/80387 Recognition ................................ .......... ................ ................ 5-8
5.4.2 80387 Emulator .......... ................. ................. ..... ............. ................ ............ 5-9
CHAPTER 6
MEMORY
INTERFACING
6.1 Memory Speed versus Performance and Cost .......... ............ ........................ 6-1
6.2 Basic Memory Interface ........... .................. ....... ..................... ........... ............. 6-1
6.2.1 PAL Devices ............................................................................................... 6-2
6.2.2 Address Latch ..... .......................................... ......... ....... ..... ........................ 6-3
6.2.3 Address Decoder ....................................................................................... 6-4
6.2.4 Data Transceiver ........................................................................................ 6-5
6.2.5 Bus Control Logic .. .......... ....... ........................... ......... ...... .......... ............... 6-6
6.2.6 EPROM Interface ....................... ...... ....... ........ ......... ......... .......... ............... 6-9
6.2.7 SRAMlnterface .......................................................................................... 6-11
6.2.8 16-Bit Interface ........................................................................................... 6-14
6.3 Dynamic RAM (DRAM) Interface ................................................................... 6-15
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